Abstract: A method of transferring a compressed web page over a computer network without affecting the existing web server applications and processes. The compressor intercepts a request from a workstation for the web page. A second request is transmitted to the server from the compressor for the original, uncompressed web page. The web page is selectively compressed in the compressor. Then the compressed web page is transmitted to the workstation. Optionally, some of the files associated web page, such as image files, are also compressed and the references to the compressed associated files is changed to reflect any change in the name of the compressed associated files.

Abstract: A method of transferring a compressed web page over a computer network without affecting the existing web server applications and processes. The compressor intercepts a request from a workstation for the web page. A second request is transmitted to the server from the compressor for the original, uncompressed web page. The web page is selectively compressed in the compressor. Then the compressed web page is transmitted to the workstation. Optionally, some of the files associated web page, such as image files, are also compressed and the references to the compressed associated files is changed to reflect any change in the name of the compressed associated files.

Abstract: A system and method for distributing power to multiple circuit boards coupled with a “system” backplane is disclosed. Separate redundant pairs of power supplies are provided for each circuit board in a load sharing arrangement. Each set of power supplies and their load, i.e. the circuit board to which they are coupled and providing power to, are isolated from the other sets. The power supplies are coupled with a second “power” backplane which interconnects the redundant power supply pairs as well as receives the input voltage and current from a source and distributes it to all of the power supplies. The power backplane is further coupled with the system backplane in a back to back arrangement to effect the connection of the power supplies with their respective loads. The redundant power supplies in combination with fault monitoring and failure handling logic identify and isolate faults, enable fail-over operation and prevent collateral damage to other system components.

Abstract: A system and method for distributing power to multiple circuit boards coupled with a “system” backplane is disclosed. Separate redundant pairs of power supplies are provided for each circuit board in a load sharing arrangement. Each set of power supplies and their load, i.e. the circuit board to which they are coupled and providing power to, are isolated from the other sets. The power supplies are coupled with a second “power” backplane which interconnects the redundant power supply pairs as well as receives the input voltage and current from a source and distributes it to all of the power supplies. The power backplane is further coupled with the system backplane in a back to back arrangement to effect the connection of the power supplies with their respective loads. The redundant power supplies in combination with fault monitoring and failure handling logic identify and isolate faults, enable fail-over operation and prevent collateral damage to other system components.

Abstract: An apparatus and method for interfacing a processor to one or more co-processors interface is disclosed. The apparatus provides a dual ported memory to be used as a message passing buffer between the processor and the co-processor. Both the processor and co-processors can interface asynchronously to the dual ported memory. Control logic monitors activity by the processor to alert the co-processors of communications by the processor written to the memory and otherwise allow the processor and co-processors to think they are interfacing directly with one another.

Abstract: An inter-processor communications interface is disclosed. The interface permits the transparent movement of data from one processor to another via a memory fabric which is connected with both processors. This permits the incoming data of a first processor to be utilized by a second processor thereby freeing that processor from having to handle incoming data. Further, the second processor can handle outgoing data exclusively, freeing the first processor from having to handle outgoing data. In this way, each direction of a bi-directional dataflow may be handled by the maximum capability of a bi-directional capable processing device.

Abstract: An architecture for intercepting and processing packets from a network is disclosed. The architecture provides both stateful and stateless processing of packets in the bi-directional network flow. Further, stateless processing is provided by a parallel arrangement of network processors while stateful processing is provided by a serial arrangement of network processors. The architecture permits leveraging existing bi-directional devices to process packets in a uni-directional flow, thereby increasing the throughput of the device. The ability to share state among the stateless processor, among the stateful processors of each packet flow direction and between the stateless and stateful processors provides for dynamic adaptability and analysis of both historical and bi-directional packet activity.

Abstract: An apparatus and method for enhancing the infrastructure of a network such as the Internet is disclosed. A packet interceptor/processor apparatus is coupled with the network so as to be able to intercept and process packets flowing over the network. Further, the apparatus provides external connectivity to other devices that wish to intercept packets as well. The apparatus applies one or more rules to the intercepted packets which execute one or more functions on a dynamically specified portion of the packet and take one or more actions with the packets. The apparatus is capable of analyzing any portion of the packet including the header and payload. Actions include releasing the packet unmodified, deleting the packet, modifying the packet, logging/storing information about the packet or forwarding the packet to an external device for subsequent processing. Further, the rules may be dynamically modified by the external devices.