Patents by Inventor Peder J. Paulson

Peder J. Paulson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8780604
    Abstract: An eFuse circuit may include a wordline, a first eFuse, a first logic gate, a first blowFET, and a first bitline discharge device. The first eFuse may have a first end coupled to the wordline and a second end. The first eFuse may have a first resistance when unblown and a second resistance when blown. The first logic gate may be coupled to the first end of the first eFuse. The first logic gate may be capable of driving enough current to blow the first eFuse. The first blowFET may have a source coupled to a first supply voltage, a gate coupled to a program signal, and a drain coupled to the second end of the first eFuse. The first bitline discharge device may have a gate coupled to the second end of the first eFuse, a source coupled to the first supply voltage, and a drain coupled to a first bitline.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: July 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chihhung Liao, Phu Nguyen, Vimal R. Patel, George F. Paulik, Peder J. Paulson, Brian J. Reed, Salvatore N. Storino
  • Publication number: 20140003120
    Abstract: An eFuse circuit may include a wordline, a first eFuse, a first logic gate, a first blowFET, and a first bitline discharge device. The first eFuse may have a first end coupled to the wordline and a second end. The first eFuse may have a first resistance when unblown and a second resistance when blown. The first logic gate may be coupled to the first end of the first eFuse. The first logic gate may be capable of driving enough current to blow the first eFuse. The first blowFET may have a source coupled to a first supply voltage, a gate coupled to a program signal, and a drain coupled to the second end of the first eFuse. The first bitline discharge device may have a gate coupled to the second end of the first eFuse, a source coupled to the first supply voltage, and a drain coupled to a first bitline.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chihhung Liao, Phu Nguyen, Vimal R. Patel, George F. Paulik, Peder J. Paulson, Brian J. Reed, Salvatore N. Storino
  • Patent number: 6000011
    Abstract: A method and apparatus for handling commands and data associated therewith includes a data buffer and a command directory. The command directory receives and stores a command from at least one command source, and freely allocates an unused portion of the data buffer to the command. The data buffer stores the data associated with the command in the allocated portion of the data buffer. Based on status information also stored by the command directory with respect to each command, routing logic in the command directory, corresponding to each command sink, identifies which commands stored in the command buffer to route to the command sink, and routes the identified commands to the command sink. The routing logic also determines a priority of the identified commands and routes the identified commands in order of priority. The command directory also uses the status information to track the processing of commands.
    Type: Grant
    Filed: December 9, 1996
    Date of Patent: December 7, 1999
    Assignee: International Business Machines Corporation
    Inventors: Donald Lee Freerksen, Farnaz Mounes-Toussi, Peder J. Paulson, John D. Irish, Lyle E. Grosbach