Patents by Inventor Pedro A. Quintero

Pedro A. Quintero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11621395
    Abstract: A memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Nathan Strutt, Albert Chen, Pedro Quintero, Oleg Golonzka
  • Patent number: 11616192
    Abstract: A memory device includes a perpendicular magnetic tunnel junction (pMTJ) stack, between a bottom electrode and a top electrode. In an embodiment, the pMTJ includes a fixed magnet, a tunnel barrier above the fixed magnet and a free magnet structure on the tunnel barrier. The free magnet structure includes a first free magnet on the tunnel barrier and a second free magnet above the first free magnet, wherein at least a portion of the free magnet proximal to an interface with the free magnet includes a transition metal. The free magnet structure having a transition metal between the first and the second free magnets advantageously improves the switching efficiency of the MTJ, while maintaining a thermal stability of at least 50 kT.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 28, 2023
    Assignee: Intel Corporation
    Inventors: Tofizur Rahman, Christopher J. Wiegand, Justin S. Brockman, Daniel G. Ouellette, Angeline K. Smith, Andrew Smith, Pedro A. Quintero, Juan G. Alzate-Vinasco, Oleg Golonzka
  • Patent number: 11462684
    Abstract: An RRAM device is disclosed. The RRAM device includes a bottom electrode, a high-k material on the bottom electrode, a top electrode, a top contact on the top electrode and an encapsulating layer of Al2O3. The encapsulating layer encapsulates the bottom electrode, the high-k material, the top electrode and the top contact.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventors: Albert Chen, Nathan Strutt, Oleg Golonzka, Pedro Quintero, Christopher J. Jezewski, Elijah V. Karpov
  • Patent number: 11380838
    Abstract: A memory device method of fabrication that includes a first electrode having a first conductive layer including titanium and nitrogen and a second conductive layer on the first conductive layer that includes tantalum and nitrogen. The memory device further includes a magnetic tunnel junction (MTJ) on the first electrode. In some embodiments, at least a portion of the first conductive layer proximal to an interface with the second conductive layer includes oxygen.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Justin Brockman, Conor Puls, Stephen Wu, Christopher Wiegand, Tofizur Rahman, Daniel Ouellette, Angeline Smith, Andrew Smith, Pedro Quintero, Juan Alzate-Vinasco, Oleg Golonzka
  • Publication number: 20200343445
    Abstract: A memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.
    Type: Application
    Filed: April 26, 2019
    Publication date: October 29, 2020
    Applicant: Intel Corporation
    Inventors: Nathan Strutt, Albert Chen, Pedro Quintero, Oleg Golonzka
  • Publication number: 20200203605
    Abstract: An RRAM device is disclosed. The RRAM device includes a bottom electrode, a high-k material on the bottom electrode, a top electrode, a top contact on the top electrode and an encapsulating layer of Al2O3. The encapsulating layer encapsulates the bottom electrode, the high-k material, the top electrode and the top contact.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Albert CHEN, Nathan STRUTT, Oleg GOLONZKA, Pedro QUINTERO, Christopher J. JEZEWSKI, Elijah V. KARPOV
  • Publication number: 20200006634
    Abstract: A memory device method of fabrication that includes a first electrode having a first conductive layer including titanium and nitrogen and a second conductive layer on the first conductive layer that includes tantalum and nitrogen. The memory device further includes a magnetic tunnel junction (MTJ) on the first electrode. In some embodiments, at least a portion of the first conductive layer proximal to an interface with the second conductive layer includes oxygen.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Justin Brockman, Conor Puls, Stephen Wu, Christopher Wiegand, Tofizur Rahman, Daniel Ouellette, Angeline Smith, Andrew Smith, Pedro Quintero, Juan Alzate-Vinasco, Oleg Golonzka
  • Publication number: 20200006635
    Abstract: A memory device includes a perpendicular magnetic tunnel junction (pMTJ) stack, between a bottom electrode and a top electrode. In an embodiment, the pMTJ includes a fixed magnet, a tunnel barrier above the fixed magnet and a free magnet structure on the tunnel barrier. The free magnet structure includes a first free magnet on the tunnel barrier and a second free magnet above the first free magnet, wherein at least a portion of the free magnet proximal to an interface with the free magnet includes a transition metal. The free magnet structure having a transition metal between the first and the second free magnets advantageously improves the switching efficiency of the MTJ, while maintaining a thermal stability of at least 50 kT.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Tofizur Rahman, Christopher J. Wiegand, Justin S. Brockman, Daniel G. Ouellette, Angeline K. Smith, Andrew Smith, Pedro A. Quintero, Juan G. Alzate-Vinasco, Oleg Golonzka
  • Publication number: 20100096043
    Abstract: A solder material is formed utilizing a transient liquid phase sintering process, where a precursor material is first formed. The precursor material comprises a plurality of metal particles including a first metal having a first melting point temperature and a second metal having a second melting point temperature, the first melting point temperature being greater than the second melting point temperature. The precursor material is heated to a process temperature (Tp) that is greater than the second melting point temperature and less than the first melting point temperature, and the precursor material is isothermally held at the process temperature (Tp) for a preselected holding period so as to form a metal alloy material having a melting point temperature that is greater than the process temperature. The solder material can be used to bond two components together in a device specified for use at an application temperature (Ta), where Ta/Tp>1.
    Type: Application
    Filed: July 10, 2009
    Publication date: April 22, 2010
    Applicant: UNIVERSITY OF MARYLAND, COLLEGE PARK
    Inventors: Patrick F. McCluskey, Pedro Quintero