Patents by Inventor Pedro Costa
Pedro Costa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12583657Abstract: A tool accessory packaging for at least one tool accessory, in particular a drill bit, includes a packaging base body which forms a receiving pocket, in particular a folded pocket, for receiving the at least one tool accessory and which is intended for receiving tool accessories with different geometries in the receiving pocket. The receiving pocket adapts to a geometry of the at least one tool accessory, at least in sections, due to its material-specific restoring force when the at least one tool accessory is arranged in the receiving pocket and fixes the at least one tool accessory in a receiving region, in particular in a non-slip manner.Type: GrantFiled: December 11, 2023Date of Patent: March 24, 2026Assignee: Robert Bosch GmbHInventors: Alexander Faeht, Florian Beck, Pedro Costa, Thomas Reissig, Tim Hoffmann, Simon Johansson
-
Publication number: 20240190633Abstract: A tool accessory packaging for at least one tool accessory, in particular a drill bit, includes a packaging base body which forms a receiving pocket, in particular a folded pocket, for receiving the tool accessory and which is intended for receiving tool accessories with different geometries in the receiving pocket. The receiving pocket adapts to a geometry of the tool accessory, at least in sections, due to its material-specific restoring force when the tool accessory is arranged in the receiving pocket and fixes the tool accessory in a receiving region, in particular in a non-slip manner.Type: ApplicationFiled: December 11, 2023Publication date: June 13, 2024Inventors: Alexander Faeht, Florian Beck, Pedro Costa, Thomas Reissig, Tim Hoffmann, Simon Johansson
-
Patent number: 11119695Abstract: A memory dispatcher, including an address decoder configured to decode a write address of received write data; a lockstep processor configured to generate, based on the decoded write address, primary and redundant memory write addresses and corresponding primary and redundant copies of the write data, if the decoded write address corresponds with a lockstep region of the memory; and a comparator coupled to the lockstep processor, and configured to compare the primary and redundant copies of the write data, and to compare the primary and redundant memory write addresses.Type: GrantFiled: March 28, 2019Date of Patent: September 14, 2021Assignee: Infineon Technologies AGInventors: Pedro Costa, Muhammad Hassan
-
Publication number: 20210085244Abstract: An articulation rigidity assessment device comprises a single-axis angular velocity sensor attachable to a limb such that an axis of measurement is parallel to a predetermined rotation axis of a bending motion imposed during a dosage administration regime of a drug in order to identify a clinically effective dose as having been administered. A data processor is configured to process an angular velocity sensor signal during the dosage administration, calculate a non-rigidity index of the articulation using the processed signal, wherein the non-rigidity index is the square root of the multiplication of the average of the angular velocity signal by the average peak value of the angular velocity signal. The device outputs feedback of the non-rigidity index at a current dose of the drug, whereby the clinically effective dose is identified as having been administered as a function of the output. A method is also disclosed.Type: ApplicationFiled: December 8, 2020Publication date: March 25, 2021Inventors: João Paulo TRIGUEIROS DA SILVA CUNHA, Pedro COSTA
-
Patent number: 10929949Abstract: A device for accessing memory configured to store an image data cube, wherein the memory has memory banks, and each memory bank has memory rows and memory columns. The device includes an input configured to receive a memory access request having a logical start address, which specifies a logical bank, a logical row, and a logical column, and a burst size; and a memory address generator configured to generate physical memory addresses based on the logical start address and the burst size, wherein any consecutive logical start addresses mapped to different memory rows are mapped to different memory banks.Type: GrantFiled: March 28, 2019Date of Patent: February 23, 2021Assignee: Infineon Technologies AGInventors: Muhammad Hassan, Pedro Costa, Andre Roger, Romain Ygnace
-
Patent number: 10856778Abstract: It is disclosed an articulation rigidity assessment device for assessing the rigidity of the articulation when a bending motion is imposed to a limb of said articulation around a predetermined rotation axis of the articulation, said device comprising: a one-axis angular velocity sensor for attaching to said limb such that the axis of measurement is parallel to the axis of rotation of the imposed bending motion; a data processor configured to process the signal of the angular velocity sensor and to distinguish between non-rigid and rigid states of the articulation using the processed angular velocity signal. The articulation may be the wrist articulation of the patient and the limb is the respective hand. The device may comprise a skin-contacting patch for applying to the limb of the patient wherein the one-axis angular velocity sensor is attached to said skin-contacting patch. The skin-contacting patch may be applied to the palm or back of the hand.Type: GrantFiled: April 14, 2016Date of Patent: December 8, 2020Assignee: INESC TEC—INSTITUTO DE ENGENHARIA DE SISTEMAS EInventors: João Paulo Trigueiros Da Silva Cunha, Pedro Costa
-
Publication number: 20200310683Abstract: A memory dispatcher, including an address decoder configured to decode a write address of received write data; a lockstep processor configured to generate, based on the decoded write address, primary and redundant memory write addresses and corresponding primary and redundant copies of the write data, if the decoded write address corresponds with a lockstep region of the memory; and a comparator coupled to the lockstep processor, and configured to compare the primary and redundant copies of the write data, and to compare the primary and redundant memory write addresses.Type: ApplicationFiled: March 28, 2019Publication date: October 1, 2020Inventors: Pedro Costa, Muhammad Hassan
-
Publication number: 20200311863Abstract: A device for accessing memory configured to store an image data cube, wherein the memory has memory banks, and each memory bank has memory rows and memory columns. The device includes an input configured to receive a memory access request having a logical start address, which specifies a logical bank, a logical row, and a logical column, and a burst size; and a memory address generator configured to generate physical memory addresses based on the logical start address and the burst size, wherein any consecutive logical start addresses mapped to different memory rows are mapped to different memory banks.Type: ApplicationFiled: March 28, 2019Publication date: October 1, 2020Inventors: Muhammad Hassan, Pedro Costa, Andre Roger, Romain Ygnace
-
Patent number: 10523190Abstract: A modulator having a pulse density modulator configured to generate from bit stream information a Pulse Density Modulation (PDM) stream based on a PDM clock; and a bit stream adjuster configured to divide the PDM clock into a PDM multi-phase clock, adjust a duration of at least one pulse of the generated PDM stream by selecting a PDM clock phase of the PDM multi-phase clock for sampling the generated PDM stream, and output an adjusted PDM stream.Type: GrantFiled: November 28, 2017Date of Patent: December 31, 2019Assignee: Infineon Technologies AGInventors: Pedro Costa, Ketan Dewan
-
Publication number: 20190165775Abstract: A modulator having a pulse density modulator configured to generate from bit stream information a Pulse Density Modulation (PDM) stream based on a PDM clock; and a bit stream adjuster configured to divide the PDM clock into a PDM multi-phase clock, adjust a duration of at least one pulse of the generated PDM stream by selecting a PDM clock phase of the PDM multi-phase clock for sampling the generated PDM stream, and output an adjusted PDM stream.Type: ApplicationFiled: November 28, 2017Publication date: May 30, 2019Inventors: Pedro Costa, Ketan Dewan
-
Patent number: 10236866Abstract: A timer including a Pulse Width Modulation (PWM) signal generator configured to generate, based on a clock, a PWM signal having a first frequency resolution; a PWM time shifter configured to receive from the PWM signal generator the PWM signal having the first frequency resolution, and output a PWM signal having a second frequency resolution, wherein the second frequency resolution is higher than the first frequency resolution; and a control monitor configured to: control the PWM time shifter to time shift rising edges or falling edges of the PWM signal by an amount corresponding with a second frequency resolution.Type: GrantFiled: April 26, 2017Date of Patent: March 19, 2019Assignee: Infineon Technologies AGInventor: Pedro Costa
-
Patent number: 10211737Abstract: In some examples, a device includes control circuitry configured to receive a first input signal, receive a second input signal, and cause gate driver circuitry to deliver a driver signal to a switch to cause the switch to deliver electrical power to an electrical load. In some examples, the control circuitry is further configured to determine whether the first input signal has an active value and determine whether the second input signal has an active value. In some examples, the control circuitry is also configured to cause the gate driver circuitry to change the driver signal across a switching cycle of the switch to increase or decrease the electrical power delivered by the switch to the electrical load in response to determining that the first input signal has the active value or in response to determining that the second input signal has the active value.Type: GrantFiled: October 11, 2017Date of Patent: February 19, 2019Assignee: Infineon Technologies AGInventors: Pedro Costa, Pablo Yelamos Ruiz
-
Publication number: 20180316336Abstract: A timer including a Pulse Width Modulation (PWM) signal generator configured to generate, based on a clock, a PWM signal having a first frequency resolution; a PWM time shifter configured to receive from the PWM signal generator the PWM signal having the first frequency resolution, and output a PWM signal having a second frequency resolution, wherein the second frequency resolution is higher than the first frequency resolution; and a control monitor configured to: control the PWM time shifter to time shift rising edges or falling edges of the PWM signal by an amount corresponding with a second frequency resolution.Type: ApplicationFiled: April 26, 2017Publication date: November 1, 2018Inventor: Pedro Costa
-
Publication number: 20180116562Abstract: It is disclosed an articulation rigidity assessment device for assessing the rigidity of the articulation when a bending motion is imposed to a limb of said articulation around a predetermined rotation axis of the articulation, said device comprising: a one-axis angular velocity sensor for attaching to said limb such that the axis of measurement is parallel to the axis of rotation of the imposed bending motion; a data processor configured to process the signal of the angular velocity sensor and to distinguish between non-rigid and rigid states of the articulation using the processed angular velocity signal. The articulation may be the wrist articulation of the patient and the limb is the respective hand. The device may comprise a skin-contacting patch for applying to the limb of the patient wherein the one-axis angular velocity sensor is attached to said skin-contacting patch. The skin-contacting patch may be applied to the palm or back of the hand.Type: ApplicationFiled: April 14, 2016Publication date: May 3, 2018Inventors: João Paulo TRIGUEIROS DA SILVA CUNHA, Pedro COSTA
-
Patent number: 9935623Abstract: The disclosure generally relates to a method and an apparatus for providing an adjustable high resolution dead time, and more specifically, to a method and an apparatus for inserting an adjustable high resolution dead time in a PWM signal. A method for inserting an adjustable high resolution dead time in a PWM signal includes receiving a clock signal at a delaying circuitry and generating, by the delaying circuitry, a plurality of phases, receiving the generated plurality of phases at a first multiplexer, and selecting and forwarding, by the first multiplexer, a first phase of the plurality of phases based on a first high resolution dead time value. The method further includes shifting a rising edge and/or a falling edge of the PWM signal using the received first phase forwarded by the first multiplexer.Type: GrantFiled: July 15, 2016Date of Patent: April 3, 2018Assignee: Infineon Technologies AGInventor: Pedro Costa
-
Publication number: 20170040988Abstract: The disclosure generally relates to a method and an apparatus for providing an adjustable high resolution dead time, and more specifically, to a method and an apparatus for inserting an adjustable high resolution dead time in a PWM signal. A method for inserting an adjustable high resolution dead time in a PWM signal includes receiving a clock signal at a delaying circuitry and generating, by the delaying circuitry, a plurality of phases, receiving the generated plurality of phases at a first multiplexer, and selecting and forwarding, by the first multiplexer, a first phase of the plurality of phases based on a first high resolution dead time value. The method further includes shifting a rising edge and/or a falling edge of the PWM signal using the received first phase forwarded by the first multiplexer.Type: ApplicationFiled: July 15, 2016Publication date: February 9, 2017Inventor: Pedro Costa
-
Patent number: 9041375Abstract: In various embodiments a controller for controlling the operation of a switched mode power supply is provided, the controller comprising: a first signal source configured to provide a first set of signals including a set signal and a clear signal, wherein the first set of signals may correspond to a first mode of operation of the switched mode power supply; a second signal source configured to provide a second set of signals including a set signal and a clear signal, wherein the second set of signals may correspond to a second mode of operation of the switched mode power supply; a selecting circuit coupled to the first signal source and to the second signal source, the selecting circuit being configured to select either the first set of signals or the second set of signals; a switching signal generating circuit coupled to the selecting circuit and configured to provide a switching signal to the switched mode power supply based on the set of signals received from the selecting circuit.Type: GrantFiled: October 30, 2012Date of Patent: May 26, 2015Assignee: INFINEON TECHNOLOGIES AGInventor: Pedro Costa
-
Patent number: D885217Type: GrantFiled: November 20, 2018Date of Patent: May 26, 2020Assignee: WATGRID LDA.Inventors: Rogério Nogueira, Lúcia Bilro, Fábio Gonçalves, Pedro Costa, Ricardo Pereira
-
Patent number: D885218Type: GrantFiled: November 20, 2018Date of Patent: May 26, 2020Assignee: WATGRID LDA.Inventors: Rogério Nogueira, Lúcia Bilro, Fábio Gonçalves, Pedro Costa, Ricardo Pereira
-
Patent number: D885948Type: GrantFiled: November 20, 2018Date of Patent: June 2, 2020Assignee: WATGRID LDA.Inventors: Rogério Nogueira, Lúcia Bilro, Fábio Gonçalves, Pedro Costa, Ricardo Pereira