Patents by Inventor Pedro E. Castillo-Borelly

Pedro E. Castillo-Borelly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100265989
    Abstract: A thermopile-based thermal detector is provided by a thermocouple, formed from a single sheet of material, which is made dissimilar with a P-doped and an N-doped junction electrically isolated via a naturally forming depletion region. The thermopile P-N sheet is uniform and planar, addressing stress and manufacturing issues. The usual non-active area of a conventional thermopile is significantly reduced or eliminated, and thus the output signal per unit diaphragm area of the detector is substantially increased, without the typical reduction in the signal-to-noise ratio. Also, a significant reduction in size of the thermal detector area is provided without a reduction in signal or signal-to-noise ratio. In an aspect, a second layer of thermocouples is axially positioned over, and connected with, a first layer of thermocouples. Additional axially stacked thermopiles can be provided within the same fabrication process. Signal processing circuitry may be electrically interconnected with the thermocouple.
    Type: Application
    Filed: July 1, 2010
    Publication date: October 21, 2010
    Applicant: DELPHI TECHNOLOGIES, INC.
    Inventors: BRIAN E. DEWES, PEDRO E. CASTILLO-BORELLY
  • Patent number: 7785002
    Abstract: A thermopile-based thermal detector is provided by a thermocouple, formed from a single sheet of material, which is made dissimilar with a P-doped and an N-doped junction electrically isolated via a naturally forming depletion region. The thermopile P-N sheet is uniform and planar, addressing stress and manufacturing issues. The usual non-active area of a conventional thermopile is significantly reduced or eliminated, and thus the output signal per unit diaphragm area of the detector is substantially increased, without the typical reduction in the signal-to-noise ratio. Also, a significant reduction in size of the thermal detector area is provided without a reduction in signal or signal-to-noise ratio. In an aspect, a second layer of thermocouples is axially positioned over, and connected with, a first layer of thermocouples. Additional axially stacked thermopiles can be provided within the same fabrication process. Signal processing circuitry may be electrically interconnected with the thermocouple.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: August 31, 2010
    Assignee: Delphi Technologies, Inc.
    Inventors: Brian E. Dewes, Pedro E. Castillo-Borelly
  • Publication number: 20080130710
    Abstract: A thermopile-based thermal detector is provided by a thermocouple, formed from a single sheet of material, which is made dissimilar with a P-doped and an N-doped junction electrically isolated via a naturally forming depletion region. The thermopile P-N sheet is uniform and planar, addressing stress and manufacturing issues. The usual non-active area of a conventional thermopile is significantly reduced or eliminated, and thus the output signal per unit diaphragm area of the detector is substantially increased, without the typical reduction in the signal-to-noise ratio. Also, a significant reduction in size of the thermal detector area is provided without a reduction in signal or signal-to-noise ratio. In an aspect, a second layer of thermocouples is axially positioned over, and connected with, a first layer of thermocouples. Additional axially stacked thermopiles can be provided within the same fabrication process. Signal processing circuitry may be electrically interconnected with the thermocouple.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 5, 2008
    Inventors: Brian E. Dewes, Pedro E. Castillo-Borelly
  • Patent number: 7335954
    Abstract: An electrostatic discharge (ESD) protection device includes a first-type substrate, a second-type well formed in the substrate and a first-type well formed in the substrate. The second-type well includes a second-type+ region formed between first and second first-type+ regions. The first-type well is formed in the substrate adjacent a first side of the second-type well. The first-type well includes first and second first-type regions with a first-type+ region and a second-type+ region formed between the first and second first-type regions. The second-type+ region of the first-type well is formed between the first-type+ region of the first-type well and the second-type well.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: February 26, 2008
    Assignee: Delphi Technolgoies, Inc.
    Inventors: Jack L. Glenn, Pedro E. Castillo-Borelly
  • Patent number: 7119326
    Abstract: A method and apparatus for evaluating the functionality and sensitivity of an infrared sensor to infrared radiation. The method and apparatus are adapted for testing an infrared sensor having a diaphragm containing a heating element and a transducer that generates an output responsive to temperature. The method entails placing the infrared sensor in a controlled environment, and then exposing the diaphragm of the sensor to different levels of thermal radiation so as to obtain outputs of the transducer at different output levels. In the absence of exposure of the diaphragm to thermal radiation, flowing current through the heating element at different input levels so that the output of the transducer returns to the different output levels obtained using thermal radiation, the input difference between the input levels can be computed and used to assess the functionality and the sensitivity of the sensor.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: October 10, 2006
    Assignee: Delphi Technologies, Inc.
    Inventors: James H. Logsdon, Pedro E. Castillo-Borelly, Abhijeet V. Chavan, Michael P. Donahue, Deron K. Slaughter
  • Patent number: 5856941
    Abstract: A cross-coupled latch circuit that is a one-time programmable latch that allows volatile temporary writes to the latch prior to permanent programming of the latch. The latch circuit includes first and second programmable FET devices that include poly-poly capacitators in series with the gate terminal of each device. A pair of PMOS FET devices combine with the programmable devices to make up the latch. The latch circuit includes other FET devices that are switched on and off depending on whether the latch is being permanently programmed, temporarily written to, or reset. A NAND gate is provided such that a logical high output on the NAND gate allows the first programmable device to be temporarily programmed with a logical one and permanently programmed with a logical zero. A NOR gate is provided such that a logical high on the NOR gate allows the second programmable device to be temporarily programmed with a logical zero and permanently programmed with a logical one.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: January 5, 1999
    Assignee: Delco Electronics Corporation
    Inventors: Mark Russell Keyse, Gregory Jon Manlove, Pedro E. Castillo-Borelly, Seyed Ramezan Zarabadi