Abstract: Using a common reference address when processing calls between a native application binary interface (ABI) and a foreign ABI. Based on a caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code and that the callee is native, or a memory range not storing native code and that the callee is foreign. Execution of a callee is initiated based on one of (i) calling the callee using the reference address within an emulator when the caller is native and the callee is foreign; (ii) calling an entry thunk when the caller is foreign and the callee is native; (iii) calling an exit thunk when the caller is native and the callee is foreign; or (iv) directly calling the callee using the reference address when the caller is native and the callee is native.

Abstract: Dynamically overriding a function based on a capability set. A computer system reads a portion of an executable image file. The portion includes a first memory address corresponding to a first callee function implementation. The first memory address was inserted into the portion by a compiler toolchain. Based on extensible metadata included in the executable image file, and based on a capability set that is specific to the computer system, the computer system determines a second memory address corresponding to a second callee function implementation. Before execution of the portion, the computer system modifies the portion to replace the first memory address with the second memory address.

Abstract: Dynamically overriding a function based on a capability set. A computer system reads a portion of an executable image file. The portion includes a first memory address corresponding to a first callee function implementation. The first memory address was inserted into the portion by a compiler toolchain. Based on extensible metadata included in the executable image file, and based on a capability set that is specific to the computer system, the computer system determines a second memory address corresponding to a second callee function implementation. Before execution of the portion, the computer system modifies the portion to replace the first memory address with the second memory address.

Abstract: A hybrid binary executable under both native processes and compatibility (e.g., emulated) processes. When the hybrid binary is loaded by a native process, the process executes a native code stream contained in the binary directly on a processor. When the hybrid binary is loaded by a compatibility process, the process executes an emulation-compatible (EC) code stream directly on a processor. The hybrid binary format supports folding of code between the native code stream and the EC code stream. The hybrid binary comprises a set of memory transformations which are applied to image data obtained from the binary when the hybrid binary executes under the compatibility process.

Abstract: Unaligned atomic memory operations on a processor using a load-store instruction set architecture (ISA) that requires aligned accesses are performed by widening the memory access to an aligned address by the next larger power of two (e.g., 4-byte access is widened to 8 bytes, and 8-byte access is widened to 16 bytes). Data processing operations supported by the load-store ISA including shift, rotate, and bitfield manipulation are utilized to modify only the bytes in the original unaligned address so that the atomic memory operations are aligned to the widened access address. The aligned atomic memory operations using the widened accesses avoid the faulting exceptions associated with unaligned access for most 4-byte and 8-byte accesses. Exception handling is performed in cases in which memory access spans a 16-byte boundary.

Abstract: Using a common reference address when processing calls among a native ABI and a foreign ABI. Based on caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code (and that the callee is native) or a memory range not storing native code (and that the callee is foreign). Execution of the callee is initiated based on one of (i) when the caller is native and when the callee is foreign, calling the callee using the reference address within an emulator; (ii) when the caller is foreign and the callee is native, calling an entry thunk; (iii) when the caller is native and the callee is foreign, calling an exit thunk; or (iv) when the caller is native and the callee is native, directly calling the callee using the reference address.

Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.

Abstract: Using a common reference address when processing calls among a native ABI and a foreign ABI. Based on caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code (and that the callee is native) or a memory range not storing native code (and that the callee is foreign). Execution of the callee is initiated based on one of (i) when the caller is native and when the callee is foreign, calling the callee using the reference address within an emulator; (ii) when the caller is foreign and the callee is native, calling an entry thunk; (iii) when the caller is native and the callee is foreign, calling an exit thunk; or (iv) when the caller is native and the callee is native, directly calling the callee using the reference address.

Abstract: A function is compiled against a first application binary interface (ABI) and a second ABI of a native first instruction set architecture (ISA). The second ABI defines context data not exceeding a size expected by a third ABI of a foreign second ISA, and uses a subset of registers of the first ISA that are mapped to registers of the second ISA. Use of the subset of registers by the second ABI results in some functions being foldable when compiled using both the first and second ABIs. First and second compiled versions of the function are identified as foldable, or not, based on whether the compiled versions match. Both the first and second compiled versions are emitted into a binary file when they are not foldable, and only one of the first or second compiled versions is emitted into the binary file when they are foldable.

Abstract: Using a common reference address when processing calls among a native ABI and a foreign ABI. Based on caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code (and that the callee is native) or a memory range not storing native code (and that the callee is foreign). Execution of the callee is initiated based on one of (i) when the caller is native and when the callee is foreign, calling the callee using the reference address within an emulator; (ii) when the caller is foreign and the callee is native, calling an entry thunk; (iii) when the caller is native and the callee is foreign, calling an exit thunk; or (iv) when the caller is native and the callee is native, directly calling the callee using the reference address.

Abstract: Unaligned atomic memory operations on a processor using a load-store instruction set architecture (ISA) that requires aligned accesses are performed by widening the memory access to an aligned address by the next larger power of two (e.g., 4-byte access is widened to 8 bytes, and 8-byte access is widened to 16 bytes). Data processing operations supported by the load-store ISA including shift, rotate, and bitfield manipulation are utilized to modify only the bytes in the original unaligned address so that the atomic memory operations are aligned to the widened access address. The aligned atomic memory operations using the widened accesses avoid the faulting exceptions associated with unaligned access for most 4-byte and 8-byte accesses. Exception handling is performed in cases in which memory access spans a 16-byte boundary.

Abstract: A function is compiled against a first application binary interface (ABI) and a second ABI of a native first instruction set architecture (ISA). The second ABI defines context data not exceeding a size expected by a third ABI of a foreign second ISA, and uses a subset of registers of the first ISA that are mapped to registers of the second ISA. Use of the subset of registers by the second ABI results in some functions being foldable when compiled using both the first and second ABIs. First and second compiled versions of the function are identified as foldable, or not, based on whether the compiled versions match. Both the first and second compiled versions are emitted into a binary file when they are not foldable, and only one of the first or second compiled versions is emitted into the binary file when they are foldable.

Abstract: Unaligned atomic memory operations on a processor using a load-store instruction set architecture (ISA) that requires aligned accesses are performed by widening the memory access to an aligned address by the next larger power of two (e.g., 4-byte access is widened to 8 bytes, and 8-byte access is widened to 16 bytes). Data processing operations supported by the load-store ISA including shift, rotate, and bitfield manipulation are utilized to modify only the bytes in the original unaligned address so that the atomic memory operations are aligned to the widened access address. The aligned atomic memory operations using the widened accesses avoid the faulting exceptions associated with unaligned access for most 4-byte and 8-byte accesses. Exception handling is performed in cases in which memory access spans a 16-byte boundary.

Abstract: A hybrid binary executable under both native processes and compatibility (e.g., emulated) processes. When the hybrid binary is loaded by a native process, the process executes a native code stream contained in the binary directly on a processor. When the hybrid binary is loaded by a compatibility process, the process executes an emulation-compatible (EC) code stream directly on a processor. When executing in a compatibility process, the EC code stream can interact with a foreign code stream that executes in an emulator. The foreign code stream can be included in the hybrid binary itself, or can be external to the hybrid binary. The hybrid binary format supports folding of code between the native code stream and the EC code stream. The hybrid binary comprises a set of memory transformations which are applied to image data obtained from the binary when the hybrid binary executes under the compatibility process.

Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.

Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.

Abstract: Unaligned atomic memory operations on a processor using a load-store instruction set architecture (ISA) that requires aligned accesses are performed by widening the memory access to an aligned address by the next larger power of two (e.g., 4-byte access is widened to 8 bytes, and 8-byte access is widened to 16 bytes). Data processing operations supported by the load-store ISA including shift, rotate, and bitfield manipulation are utilized to modify only the bytes in the original unaligned address so that the atomic memory operations are aligned to the widened access address. The aligned atomic memory operations using the widened accesses avoid the faulting exceptions associated with unaligned access for most 4-byte and 8-byte accesses. Exception handling is performed in cases in which memory access spans a 16-byte boundary.

Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.

Abstract: A computing system includes one or more processors and a storage device that stores computer executable instructions that can be executed by the processors to cause the computing system to perform the following. The system generates a work tracking information ticket for a first system entity. The system assigns the work tracking information ticket to the first system entity. The system passes the work tracking information ticket to one or more second system entities. The system validates the work tracking information ticket. The validated work tracking information ticket informs that the one or more second system entities are performing work on behalf of the first system entity.

Abstract: Among other things, one or more techniques and/or systems are provided for controlling resource access for background tasks. For example, a background task created by an application may utilize a resource (e.g., CPU cycles, bandwidth usage, etc.) by consuming resource allotment units from an application resource pool. Once the application resource pool is exhausted, the background task is generally restricted from utilizing the resource. However, the background task may also utilize global resource allotment units from a global resource pool shared by a plurality of applications to access the resource. Once the global resource pool is exhausted, unless the background task is a guaranteed background task which can consume resources regardless of resource allotment states of resource pools, the background task may be restricted from utilizing the resource until global resource allotment units within the global resource pool and/or resource allotment units within the application resource pool are replenished.