Patents by Inventor Pedro Miguel Sequeira de Justo Teixeira

Pedro Miguel Sequeira de Justo Teixeira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11403100
    Abstract: Using a common reference address when processing calls among a native ABI and a foreign ABI. Based on caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code (and that the callee is native) or a memory range not storing native code (and that the callee is foreign). Execution of the callee is initiated based on one of (i) when the caller is native and when the callee is foreign, calling the callee using the reference address within an emulator; (ii) when the caller is foreign and the callee is native, calling an entry thunk; (iii) when the caller is native and the callee is foreign, calling an exit thunk; or (iv) when the caller is native and the callee is native, directly calling the callee using the reference address.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 2, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Darek Josip Mihocka, Clarence Siu Yeen Dang, Pedro Miguel Sequeira De Justo Teixeira, Pavlo Lebedynskiy, James David Cleary, Jon Robert Berry, YongKang Zhu, Tiansheng Tan
  • Patent number: 11379195
    Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: July 5, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Henry Morgan, Ten Tzen, Christopher Martin McKinsey, YongKang Zhu, Terry Mahaffey, Pedro Miguel Sequeira de Justo Teixeira, Arun Upadhyaya Kishan, Youssef M. Barakat
  • Patent number: 11366666
    Abstract: Using a common reference address when processing calls among a native ABI and a foreign ABI. Based on caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code (and that the callee is native) or a memory range not storing native code (and that the callee is foreign). Execution of the callee is initiated based on one of (i) when the caller is native and when the callee is foreign, calling the callee using the reference address within an emulator; (ii) when the caller is foreign and the callee is native, calling an entry thunk; (iii) when the caller is native and the callee is foreign, calling an exit thunk; or (iv) when the caller is native and the callee is native, directly calling the callee using the reference address.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 21, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Darek Josip Mihocka, Clarence Siu Yeen Dang, Pedro Miguel Sequeira De Justo Teixeira, Pavlo Lebedynskiy, James David Cleary, Jon Robert Berry, YongKang Zhu, Tiansheng Tan
  • Publication number: 20220137942
    Abstract: A function is compiled against a first application binary interface (ABI) and a second ABI of a native first instruction set architecture (ISA). The second ABI defines context data not exceeding a size expected by a third ABI of a foreign second ISA, and uses a subset of registers of the first ISA that are mapped to registers of the second ISA. Use of the subset of registers by the second ABI results in some functions being foldable when compiled using both the first and second ABIs. First and second compiled versions of the function are identified as foldable, or not, based on whether the compiled versions match. Both the first and second compiled versions are emitted into a binary file when they are not foldable, and only one of the first or second compiled versions is emitted into the binary file when they are foldable.
    Type: Application
    Filed: December 14, 2021
    Publication date: May 5, 2022
    Inventors: Pedro Miguel SEQUEIRA DE JUSTO TEIXEIRA, Darek Josip MIHOCKA, Jon Robert BERRY, Russell Charles HADLEY, James David CLEARY, Clarence Siu Yeen DANG
  • Publication number: 20220066780
    Abstract: Using a common reference address when processing calls among a native ABI and a foreign ABI. Based on caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code (and that the callee is native) or a memory range not storing native code (and that the callee is foreign). Execution of the callee is initiated based on one of (i) when the caller is native and when the callee is foreign, calling the callee using the reference address within an emulator; (ii) when the caller is foreign and the callee is native, calling an entry thunk; (iii) when the caller is native and the callee is foreign, calling an exit thunk; or (iv) when the caller is native and the callee is native, directly calling the callee using the reference address.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 3, 2022
    Inventors: Darek Josip MIHOCKA, Clarence Siu Yeen DANG, Pedro Miguel SEQUEIRA DE JUSTO TEIXEIRA, Pavlo LEBEDYNSKIY, James David CLEARY, Jon Robert BERRY, YongKang ZHU, Tiansheng TAN
  • Publication number: 20220027159
    Abstract: Unaligned atomic memory operations on a processor using a load-store instruction set architecture (ISA) that requires aligned accesses are performed by widening the memory access to an aligned address by the next larger power of two (e.g., 4-byte access is widened to 8 bytes, and 8-byte access is widened to 16 bytes). Data processing operations supported by the load-store ISA including shift, rotate, and bitfield manipulation are utilized to modify only the bytes in the original unaligned address so that the atomic memory operations are aligned to the widened access address. The aligned atomic memory operations using the widened accesses avoid the faulting exceptions associated with unaligned access for most 4-byte and 8-byte accesses. Exception handling is performed in cases in which memory access spans a 16-byte boundary.
    Type: Application
    Filed: October 4, 2021
    Publication date: January 27, 2022
    Inventors: Darek MIHOCKA, Arun Upadhyaya KISHAN, Pedro Miguel SEQUEIRA DE JUSTO TEIXEIRA
  • Patent number: 11231918
    Abstract: A function is compiled against a first application binary interface (ABI) and a second ABI of a native first instruction set architecture (ISA). The second ABI defines context data not exceeding a size expected by a third ABI of a foreign second ISA, and uses a subset of registers of the first ISA that are mapped to registers of the second ISA. Use of the subset of registers by the second ABI results in some functions being foldable when compiled using both the first and second ABIs. First and second compiled versions of the function are identified as foldable, or not, based on whether the compiled versions match. Both the first and second compiled versions are emitted into a binary file when they are not foldable, and only one of the first or second compiled versions is emitted into the binary file when they are foldable.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 25, 2022
    Assignee: MICROSOFT TECHNOLOGLY LICENSING, LLC
    Inventors: Pedro Miguel Sequeira De Justo Teixeira, Darek Josip Mihocka, Jon Robert Berry, Russell Charles Hadley, James David Cleary, Clarence Siu Yeen Dang
  • Patent number: 11163575
    Abstract: Unaligned atomic memory operations on a processor using a load-store instruction set architecture (ISA) that requires aligned accesses are performed by widening the memory access to an aligned address by the next larger power of two (e.g., 4-byte access is widened to 8 bytes, and 8-byte access is widened to 16 bytes). Data processing operations supported by the load-store ISA including shift, rotate, and bitfield manipulation are utilized to modify only the bytes in the original unaligned address so that the atomic memory operations are aligned to the widened access address. The aligned atomic memory operations using the widened accesses avoid the faulting exceptions associated with unaligned access for most 4-byte and 8-byte accesses. Exception handling is performed in cases in which memory access spans a 16-byte boundary.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: November 2, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Darek Mihocka, Arun Upadhyaya Kishan, Pedro Miguel Sequeira De Justo Teixeira
  • Patent number: 11042422
    Abstract: A hybrid binary executable under both native processes and compatibility (e.g., emulated) processes. When the hybrid binary is loaded by a native process, the process executes a native code stream contained in the binary directly on a processor. When the hybrid binary is loaded by a compatibility process, the process executes an emulation-compatible (EC) code stream directly on a processor. When executing in a compatibility process, the EC code stream can interact with a foreign code stream that executes in an emulator. The foreign code stream can be included in the hybrid binary itself, or can be external to the hybrid binary. The hybrid binary format supports folding of code between the native code stream and the EC code stream. The hybrid binary comprises a set of memory transformations which are applied to image data obtained from the binary when the hybrid binary executes under the compatibility process.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 22, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Pavlo Lebedynskiy, Pedro Miguel Sequeira De Justo Teixeira, Darek Josip Mihocka, Jon Robert Berry, Clarence Siu Yeen Dang, Tiansheng Tan, James David Cleary, Yongkang Zhu, Theodore Maxwell Thomas, Ben Niu, Russell Charles Hadley
  • Publication number: 20210089282
    Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.
    Type: Application
    Filed: December 3, 2020
    Publication date: March 25, 2021
    Inventors: Henry MORGAN, Ten TZEN, Christopher Martin MCKINSEY, YongKang ZHU, Terry MAHAFFEY, Pedro Miguel Sequeira de Justo TEIXEIRA, Arun Upadhyaya KISHAN, Youssef M. BARAKAT
  • Patent number: 10884720
    Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: January 5, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Henry Morgan, Ten Tzen, Christopher Martin McKinsey, YongKang Zhu, Terry Mahaffey, Pedro Miguel Sequeira de Justo Teixeira, Arun Upadhyaya Kishan, Youssef M. Barakat
  • Publication number: 20200319888
    Abstract: Unaligned atomic memory operations on a processor using a load-store instruction set architecture (ISA) that requires aligned accesses are performed by widening the memory access to an aligned address by the next larger power of two (e.g., 4-byte access is widened to 8 bytes, and 8-byte access is widened to 16 bytes). Data processing operations supported by the load-store ISA including shift, rotate, and bitfield manipulation are utilized to modify only the bytes in the original unaligned address so that the atomic memory operations are aligned to the widened access address. The aligned atomic memory operations using the widened accesses avoid the faulting exceptions associated with unaligned access for most 4-byte and 8-byte accesses. Exception handling is performed in cases in which memory access spans a 16-byte boundary.
    Type: Application
    Filed: April 3, 2019
    Publication date: October 8, 2020
    Inventors: Darek MIHOCKA, Arun Upadhyaya KISHAN, Pedro Miguel SEQUEIRA DE JUSTO TEIXEIRA
  • Publication number: 20200110587
    Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.
    Type: Application
    Filed: October 4, 2018
    Publication date: April 9, 2020
    Inventors: Henry MORGAN, Ten TZEN, Christopher Martin MCKINSEY, YongKang ZHU, Terry MAHAFFEY, Pedro Miguel Sequeira de Justo TEIXEIRA, Arun Upadhyaya KISHAN, Youssef M. BARAKAT
  • Patent number: 10339295
    Abstract: A computing system includes one or more processors and a storage device that stores computer executable instructions that can be executed by the processors to cause the computing system to perform the following. The system generates a work tracking information ticket for a first system entity. The system assigns the work tracking information ticket to the first system entity. The system passes the work tracking information ticket to one or more second system entities. The system validates the work tracking information ticket. The validated work tracking information ticket informs that the one or more second system entities are performing work on behalf of the first system entity.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: July 2, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jon Robert Berry, Youssef Barakat, Yevgeniy M. Bak, Mehmet Iyigun, Pedro Miguel Sequeira de Justo Teixeira
  • Patent number: 9952903
    Abstract: Among other things, one or more techniques and/or systems are provided for controlling resource access for background tasks. For example, a background task created by an application may utilize a resource (e.g., CPU cycles, bandwidth usage, etc.) by consuming resource allotment units from an application resource pool. Once the application resource pool is exhausted, the background task is generally restricted from utilizing the resource. However, the background task may also utilize global resource allotment units from a global resource pool shared by a plurality of applications to access the resource. Once the global resource pool is exhausted, unless the background task is a guaranteed background task which can consume resources regardless of resource allotment states of resource pools, the background task may be restricted from utilizing the resource until global resource allotment units within the global resource pool and/or resource allotment units within the application resource pool are replenished.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: April 24, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Arun Kishan, Hari Pulapaka, Alain Gefflaut, Alex Bendetov, Pedro Miguel Sequeira de Justo Teixeira
  • Publication number: 20180032378
    Abstract: A computing system includes one or more processors and a storage device that stores computer executable instructions that can be executed by the processors to cause the computing system to perform the following. The system generates a work tracking information ticket for a first system entity. The system assigns the work tracking information ticket to the first system entity. The system passes the work tracking information ticket to one or more second system entities. The system validates the work tracking information ticket. The validated work tracking information ticket informs that the one or more second system entities are performing work on behalf of the first system entity.
    Type: Application
    Filed: July 28, 2016
    Publication date: February 1, 2018
    Inventors: Jon Robert Berry, Youssef Barakat, Yevgeniy M. Bak, Mehmet lyigun, Pedro Miguel Sequeira de Justo Teixeira
  • Publication number: 20170024243
    Abstract: One or more systems and/or techniques are provided for background task management. A background manager may receive a notification from a background task that the background task is waiting for an event, and may also receive a waitable object from the background task, where the waitable object is used by the background task to wait for the event. Responsive to the waitable object not being triggered within a period of time, the background manager may implement a power management policy for a computing device hosting the background task.
    Type: Application
    Filed: July 22, 2015
    Publication date: January 26, 2017
    Inventors: Arun U. Kishan, Pedro Miguel Sequeira de Justo Teixeira, Arsalan Ahmad, Alain Gefflaut, James Schwartz, JR.
  • Publication number: 20160034308
    Abstract: Among other things, one or more techniques and/or systems are provided for controlling resource access for background tasks. For example, a background task created by an application may utilize a resource (e.g., CPU cycles, bandwidth usage, etc.) by consuming resource allotment units from an application resource pool. Once the application resource pool is exhausted, the background task is generally restricted from utilizing the resource. However, the background task may also utilize global resource allotment units from a global resource pool shared by a plurality of applications to access the resource. Once the global resource pool is exhausted, unless the background task is a guaranteed background task which can consume resources regardless of resource allotment states of resource pools, the background task may be restricted from utilizing the resource until global resource allotment units within the global resource pool and/or resource allotment units within the application resource pool are replenished.
    Type: Application
    Filed: October 14, 2015
    Publication date: February 4, 2016
    Inventors: Arun Kishan, Hari Pulapaka, Alain Geffaut, Alex Bendetov, Pedro Miguel Sequeira de Justo Teixeira
  • Patent number: 9164803
    Abstract: Among other things, one or more techniques and/or systems are provided for controlling resource access for background tasks. For example, a background task created by an application may utilize a resource (e.g., CPU cycles, bandwidth usage, etc.) by consuming resource allotment units from an application resource pool. Once the application resource pool is exhausted, the background task is generally restricted from utilizing the resource. However, the background task may also utilize global resource allotment units from a global resource pool shared by a plurality of applications to access the resource. Once the global resource pool is exhausted, unless the background task is a guaranteed background task which can consume resources regardless of resource allotment states of resource pools, the background task may be restricted from utilizing the resource until global resource allotment units within the global resource pool and/or resource allotment units within the application resource pool are replenished.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: October 20, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Arun Kishan, Hari Pulapaka, Alain Gefflaut, Alex Bendetov, Pedro Miguel Sequeira de Justo Teixeira
  • Patent number: 8677360
    Abstract: Various embodiments provide techniques for managing threads based on a thread history. In at least some embodiments, a behavior associated with currently existing threads is observed and a thread-related action is performed. A result of the thread-related action with respect to the currently existing threads, resources associated with the currently existing threads (e.g., hardware and/or data resources), and/or other threads, is then observed. A thread history is recorded (e.g., as part of a thread history database) that includes the behavior associated with the currently existing threads, the thread related action that was performed, and the result of the thread-related action. The thread history can include information about multiple different thread behaviors and can be referenced to determine whether to perform thread-related actions in response to other observed thread behaviors.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: March 18, 2014
    Assignee: Microsoft Corporation
    Inventors: Pedro Miguel Sequeira de Justo Teixeira, Arun U. Kishan