Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.

Abstract: A method of correcting one or more errors in a memory device, the method performed by one or more controllers. The method may receive data. The method may further write bits at a memory location to a first state. The method may further read respective values of the bits at the memory location. The method may further determine an error correction based on the respective values. The method may further write the received data to the memory location as received data or inverted data, based on the error correction.

Abstract: The present disclosure is drawn to, among other things, a method for programming a memory device comprising a plurality of memory arrays. The method may include receiving a command to program one or more of the plurality of memory arrays and programming the one or more of the plurality of memory arrays based on the command. The method may optionally include erasing the one or more of the plurality of memory arrays prior to the programming.

Abstract: A medical image processing apparatus includes a memory storing training medical images, each annotated with respective weak supervision annotation information relating to at least one object represented in the training medical image, the at least one object comprising an anatomical object, a pathology, or a medical device; and processing circuitry configured to use the plurality of training medical images to train a deep learning network to perform a task, wherein the training of the deep learning network includes training a compositional latent representation comprising a plurality of kernels, wherein the training of the compositional latent network includes using the weak supervision annotation information to provide weak supervision of the training of the computational latent representation, thereby guiding the compositional latent representation towards a representation in which different ones of the kernels are representative of different objects, the different objects comprising at least one anatomical

Abstract: The present disclosure is drawn to, among other things, a method for programming a memory device comprising a plurality of memory arrays. The method may include receiving a command to program one or more of the plurality of memory arrays and programming the one or more of the plurality of memory arrays based on the command. The method may optionally include erasing the one or more of the plurality of memory arrays prior to the programming.

Abstract: A data processing apparatus comprises: a memory configured to store a trained model; and processing circuitry configured to: receive at least one dataset that comprises d variables and n samples; determine variances associated with the variables by processing the dataset using the model; determine an order of the variables based on the determined variances, including iteratively removing at least one node or variable represented by said at least one node thereby to determine the order.

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.

Abstract: The present disclosure is drawn to, among other things, a method for programming a memory device comprising a plurality of memory arrays. The method may include receiving a command to program one or more of the plurality of memory arrays and programming the one or more of the plurality of memory arrays based on the command. The method may optionally include erasing the one or more of the plurality of memory arrays prior to the programming.

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.

Abstract: A bow and arrow hunting accessory device having a mounting post assembly with a sidewall, and mounting screws that insert into a tree. Further having a swivel bar assembly, and a mounting arm assembly with an accessory support arm to support a hunting bow. The mounting post assembly further has a shaft. The swivel bar assembly has a housing with a hole. The hole receives the shaft when the swivel bar assembly mounts onto the mounting post assembly. The swivel bar assembly has an elongated housing with extension holes. The mounting arm assembly has a mounting arm having an actuating pin. The elongated housing receives the mounting arm, and any of the extension holes receives the actuating pin. The mounting arm assembly has a wind vane. Further having a clamp assembly that secures an umbrella.

Abstract: Methods and systems for addressing threshold voltage shifts of memory cells. A method includes reading a pattern of data from a first plurality of memory cells, comparing the read of the pattern of data with a known pattern of data using a reference, and if the read of the pattern of data and the known pattern of data do not match, adjusting the reference to find a reference level that results in a matching of a read of the pattern of data and the known pattern of data. Thereafter, trim sector data is read into a second plurality of memory cells using the adjusted reference level.

Abstract: Methods and systems for addressing threshold voltage shifts of memory cells. A method includes reading a pattern of data from a first plurality of memory cells, comparing the read of the pattern of data with a known pattern of data using a reference, and if the read of the pattern of data and the known pattern of data do not match, adjusting the reference to find a reference level that results in a matching of a read of the pattern of data and the known pattern of data. Thereafter, trim sector data is read into a second plurality of memory cells using the adjusted reference level.