Abstract: A database management system for use in designing integrated circuit chips. A large number of designers and users are given concurrent access to design data stored in a Master Table by providing each designer with a private copy of the Master Table called the designer's Virtual Table. Each designer can independently alter data displayed from the designer's Virtual Table without interfering with other designers. Whenever a designer alters the displayed data, the displayed row containing the altered data is written to the Master Table and the designer's Virtual Table, provided that the Master Table row's time-date stamp matches the corresponding Virtual Table row's time-date stamp. If the time-date stamps do not match, then the Master Table row is copied into the Virtual Table, the designer receives an error message, and the designer is allowed to update the corrected row.