Patents by Inventor Peggy Irelan

Peggy Irelan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240095315
    Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement license management solutions for software defined silicon (SDSi) products are disclosed. Example license management solutions disclosed herein include, but are not limited to, virtual resource migration using SDSi, resource configuration management using SDSi, hardware self-configuration using SDSi, reduced footprint agents using SDSi, performing SDSi usage evaluation and corresponding license transfer responsive to detected and/or predicted failures, transferring node locked SDSi licenses, transfer of SDSi licenses without a trusted license server, community license generation, expirable SDSi licenses via a reliable clock, non-node locked licenses via blockchain, and activating hardware features with a pre-generated hardware license.
    Type: Application
    Filed: September 25, 2023
    Publication date: March 21, 2024
    Inventors: Katalin Bartfai-Walcott, Mariusz Oriol, Vasudevan Srinivasan, Peggy Irelan, Mariusz Stepka, Kaitlin Murphy, Bharat Pillilli, Mark Baldwin, Mateusz Bronk, Fariaz Karim, Arkadiusz Berent, Vasuki Chilukuri
  • Patent number: 9372764
    Abstract: Event counter checkpointing and restoring is disclosed. In one implementation, a processor includes a first event counter to count events that occur during execution within the processor, event counter checkpoint logic, communicably coupled with the first event counter, to store, prior to a transactional execution of the processor, a value of the first event counter, a second event counter to count events prior to and during the transactional execution, wherein the second event counter is to increment without resetting after the transactional execution is aborted, event count restore logic to restore the first event counter to the stored value after the transactional execution is aborted, and tuning logic to determine, in response to aborting of the transactional execution, a number of the events that occurred during the transactional execution based on the stored value of the first event counter and a value of the second event counter.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: June 21, 2016
    Assignee: Intel Corporation
    Inventors: Laura A. Knauth, Ravi Rajwar, Konrad K. Lai, Martin G. Dixon, Peggy Irelan
  • Publication number: 20150089286
    Abstract: Event counter checkpointing and restoring is disclosed. In one implementation, a processor includes a first event counter to count events that occur during execution within the processor, event counter checkpoint logic, communicably coupled with the first event counter, to store, prior to a transactional execution of the processor, a value of the first event counter, a second event counter to count events prior to and during the transactional execution, wherein the second event counter is to increment without resetting after the transactional execution is aborted, event count restore logic to restore the first event counter to the stored value after the transactional execution is aborted, and tuning logic to determine, in response to aborting of the transactional execution, a number of the events that occurred during the transactional execution based on the stored value of the first event counter and a value of the second event counter.
    Type: Application
    Filed: November 26, 2014
    Publication date: March 26, 2015
    Inventors: Laura A. Knauth, Ravi Rajwar, Konrad K. Lai, Martin G. Dixon, Peggy Irelan
  • Patent number: 8924692
    Abstract: A method of one aspect may include storing an event count of an event counter that counts events that occur during execution within a logic device. The method may further include restoring the event counter to the stored event count after the event counter has counted additional events. Other methods are also disclosed. Apparatus, systems, and machine-readable medium having software are also disclosed.
    Type: Grant
    Filed: December 26, 2009
    Date of Patent: December 30, 2014
    Assignee: Intel Corporation
    Inventors: Laura A. Knauth, Ravi Rajwar, Konrad K. Lai, Martin G. Dixon, Peggy Irelan
  • Publication number: 20130179668
    Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.
    Type: Application
    Filed: March 6, 2013
    Publication date: July 11, 2013
    Inventors: RAVI RAJWAR, PETER LACHNER, LAURA KNAUTH, KONRAD LAI, PEGGY IRELAN
  • Publication number: 20110161639
    Abstract: A method of one aspect may include storing an event count of an event counter that counts events that occur during execution within a logic device. The method may further include restoring the event counter to the stored event count after the event counter has counted additional events. Other methods are also disclosed. Apparatus, systems, and machine-readable medium having software are also disclosed.
    Type: Application
    Filed: December 26, 2009
    Publication date: June 30, 2011
    Inventors: Laura A. Knauth, Ravi Rajwar, Konrad K. Lai, Martin G. Dixon, Peggy Irelan