Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.

Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.

Abstract: A method includes forming a semiconductor fin protruding higher than a top surface of an isolation region. The semiconductor fin overlaps a semiconductor strip, and the semiconductor strip contacts the isolation region. The method further includes forming a gate stack on a sidewall and a top surface of a first portion of the semiconductor fin, and etching the semiconductor fin and the semiconductor strip to form a trench. The trench has an upper portion in the semiconductor fin and a lower portion in the semiconductor strip. A semiconductor region is grown in the lower portion of the trench. Process gases used for growing the semiconductor region are free from both of n-type dopant-containing gases and p-type dopant-containing gases. A source/drain region is grown in the upper portion of the trench, wherein the source/drain region includes a p-type or an n-type dopant.

Abstract: A semiconductor package includes a package substrate having a top surface and an opposing bottom surface. The package substrate includes a top build-up wiring layer and an upper dielectric layer covering the top build-up wiring layer. A semiconductor device and a passive component are mounted on the top surface of the package substrate in a side-by-side manner. A molding compound encapsulates the semiconductor device and the passive component on the top surface of the package substrate. A cavity is disposed between the passive component and the top surface of the package substrate.

Abstract: Embodiments described herein relate to process systems for cleaning semiconductor process chamber components. In one example, a process system include a process chamber having process chamber components. The process chamber components include a substrate support disposed within a chamber volume of the process chamber. A gas distribution assembly faces the substrate support. A gas baffle is fluidly coupled to the gas distribution assembly. A sensor system is coupled to the process chamber and is configured to monitor at least one characteristic of the volume of the process chamber. A dynamic gas assist is fluidly coupled to the gas baffle and is communicatively coupled to the sensor.

Abstract: A semiconductor device includes a substrate, a first gate, a plurality of second gates and a resistor. The substrate is defined with an active region and a resistor region. The first gate is disposed in the active region. The first gate has a first length extending along a first direction and a second length extending along a second direction. The plurality of second gates are disposed in the resistor region. Each of the second gates has a third length extending along the first direction and a fourth length extending along the second direction. The first length is equal to the third length, and the second length is equal to the fourth length. The resistor is disposed on the plurality of second gates.

Abstract: A method includes forming a semiconductor fin protruding higher than a top surface of an isolation region. The semiconductor fin overlaps a semiconductor strip, and the semiconductor strip contacts the isolation region. The method further includes forming a gate stack on a sidewall and a top surface of a first portion of the semiconductor fin, and etching the semiconductor fin and the semiconductor strip to form a trench. The trench has an upper portion in the semiconductor fin and a lower portion in the semiconductor strip. A semiconductor region is grown in the lower portion of the trench. Process gases used for growing the semiconductor region are free from both of n-type dopant-containing gases and p-type dopant-containing gases. A source/drain region is grown in the upper portion of the trench, wherein the source/drain region includes a p-type or an n-type dopant.

Abstract: Embodiments described herein relate to process systems for cleaning semiconductor process chamber components. The process systems include a process chamber having process chamber components. The process chamber components include a substrate support disposed within a chamber volume of the process chamber. A gas distribution assembly faces the substrate support. A gas baffle is fluidly coupled to the gas distribution assembly. A sensor system is coupled to the process chamber and is configured to monitor at least one characteristic of the volume of the process chamber. A dynamic gas assist is fluidly coupled to the gas baffle and is communicatively coupled to the sensor.

Abstract: Embodiments described herein relate to process systems for cleaning semiconductor process chamber components. The process systems include a process chamber having process chamber components. The process chamber components include a substrate support disposed within a chamber volume of the process chamber. A gas distribution assembly faces the substrate support. A gas baffle is fluidly coupled to the gas distribution assembly. A sensor system is coupled to the process chamber and is configured to monitor at least one characteristic of the volume of the process chamber. A dynamic gas assist is fluidly coupled to the gas baffle and is communicatively coupled to the sensor.

Abstract: A method for forming a silicon oxide film on a step formed on a substrate includes: (a) designing a topology of a final silicon oxide film by preselecting a target portion of an initial silicon nitride film to be selectively deposited or removed or reformed with reference to a non-target portion of the initial silicon nitride film resulting in the final silicon oxide film; and (b) forming the initial silicon nitride film and the final silicon oxide film on the surfaces of the step according to the topology designed in process (a), wherein the initial silicon nitride film is deposited by ALD using a silicon-containing precursor containing halogen, and the initial silicon nitride film is converted to the final silicon oxide film by oxidizing the initial silicon nitride film without further depositing a film wherein a Si—N bond in the initial silicon nitride film is converted to a Si—O bond.

Abstract: A method for forming a silicon oxide film on a step formed on a substrate includes: (a) designing a topology of a final silicon oxide film by preselecting a target portion of an initial silicon nitride film to be selectively deposited or removed or reformed with reference to a non-target portion of the initial silicon nitride film resulting in the final silicon oxide film; and (b) forming the initial silicon nitride film and the final silicon oxide film on the surfaces of the step according to the topology designed in process (a), wherein the initial silicon nitride film is deposited by ALD using a silicon-containing precursor containing halogen, and the initial silicon nitride film is converted to the final silicon oxide film by oxidizing the initial silicon nitride film without further depositing a film wherein a Si—N bond in the initial silicon nitride film is converted to a Si—O bond.

Abstract: A substrate wafer composed of a hexagonal single crystal material including a C crystalline plane, an A crystalline plane, and an M-axis direction includes a top surface is a C-axis plane; a first side connecting to the aforementioned top surface and being substantially a curve line viewing from the direction perpendicular to the aforementioned C crystalline plane and including a curvature center; and a second side connecting to the aforementioned first side; and wherein there is a line segment defined by a shortest distance between the aforementioned second side and the aforementioned curvature center, and the aforementioned line segment is not parallel with the aforementioned M-axis direction.

Abstract: A substrate wafer composed of a hexagonal single crystal material including a C crystalline plane, an A crystalline plane, and an M-axis direction includes a top surface is a C-axis plane; a first side connecting to the aforementioned top surface and being substantially a curve line viewing from the direction perpendicular to the aforementioned C crystalline plane and including a curvature center; and a second side connecting to the aforementioned first side; and wherein there is a line segment defined by a shortest distance between the aforementioned second side and the aforementioned curvature center, and the aforementioned line segment is not parallel with the aforementioned M-axis direction.

Abstract: A method of manufacturing a light-emitting diode comprises the steps of providing a substrate comprising an upper surface and a bottom surface opposite to the upper surface; providing a semiconductor stack layer on the upper surface, wherein the semiconductor stack layer comprises a first type semiconductor layer having a first surface, a light-emitting layer on the first type semiconductor layer for emitting light, and a second type semiconductor layer on the light-emitting layer; treating the first surface to form a second surface, wherein the second surface is flatter than the first surface; and providing a laser beam through the second surface to cut the substrate.

Abstract: A method of manufacturing a light-emitting diode comprises the steps of providing a substrate comprising an upper surface and a bottom surface opposite to the upper surface; providing a semiconductor stack layer on the upper surface, wherein the semiconductor stack layer comprises a first type semiconductor layer having a first surface, a light-emitting layer on the first type semiconductor layer for emitting light, and a second type semiconductor layer on the light-emitting layer; treating the first surface to form a second surface, wherein the second surface is flatter than the first surface; and providing a laser beam through the second surface to cut the substrate.

Abstract: A light-emitting diode includes a substrate, the substrate including an upper surface, a bottom surface opposite to the upper surface, and a side surface; a first type semiconductor layer on the upper surface, wherein the first type semiconductor layer includes a first portion and a second portion, and the second portion includes an edge surrounding the first portion; a light-emitting layer on the first portion; and a second type semiconductor layer on the light-emitting layer, wherein the second portion includes a first surface and a second surface, and a first distance is between the first surface and the upper surface, and a second distance is between the second surface and the upper surface and is smaller than the first distance; wherein the first surface is rougher than the second surface, and the second surface is located at the edge.

Abstract: A light-emitting diode, comprising: a substrate, the substrate comprising an upper surface, a bottom surface opposite to the upper surface, and a side surface; a first type semiconductor layer on the upper surface, wherein the first type semiconductor layer comprises a first portion and a second portion, and the second portion comprises an edge surrounding the first portion; a light-emitting layer on the first portion; and a second type semiconductor layer on the light-emitting layer, wherein the second portion comprising a first surface and a second surface, and a first distance is between the first surface and the upper surface, and a second distance is between the second surface and the upper surface and is smaller than the first distance; wherein the first surface is rougher than the second surface, and the second surface is located at the edge.