Patents by Inventor Pei-Ching Yeh

Pei-Ching Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10276443
    Abstract: A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. A mask layer is disposed on a top surface of the fin structure. An organic dielectric layer covers the substrate, the fin structure and the mask layer. A first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Then a second etching process is performed to remove the fin structure. The first etching process is preferably an anisotropic etching process, and the second etching process is an isotropic etching process.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: April 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Chi Chen, Chih-Chung Chen, An-Chi Liu, Chih-Yueh Li, Pei-Ching Yeh, Tsung-Chieh Yang
  • Publication number: 20180226403
    Abstract: A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. A mask layer is disposed on a top surface of the fin structure. An organic dielectric layer covers the substrate, the fin structure and the mask layer. A first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Then a second etching process is performed to remove the fin structure. The first etching process is preferably an anisotropic etching process, and the second etching process is an isotropic etching process.
    Type: Application
    Filed: February 28, 2017
    Publication date: August 9, 2018
    Inventors: Shin-Chi Chen, Chih-Chung Chen, An-Chi Liu, Chih-Yueh Li, Pei-Ching Yeh, Tsung-Chieh Yang
  • Patent number: 9748333
    Abstract: A semiconductor pattern structure includes a substrate, an input/output (I/O) region defined on the substrate, a core region defined on the substrate, a dummy region defined on the substrate, and a gate electrode formed on the substrate. The dummy region is formed between the I/O region and the core region. The gate electrode crosses the I/O region and covers a portion of the dummy region.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: August 29, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Chi Chen, Chih-Yueh Li, Pei-Ching Yeh, Chih-Jen Lin
  • Publication number: 20160148878
    Abstract: A semiconductor pattern structure includes a substrate, an input/output (I/O) region defined on the substrate, a core region defined on the substrate, a dummy region defined on the substrate, and a gate electrode formed on the substrate. The dummy region is formed between the I/O region and the core region. The gate electrode crosses the I/O region and covers a portion of the dummy region.
    Type: Application
    Filed: December 26, 2014
    Publication date: May 26, 2016
    Inventors: Shin-Chi Chen, Chih-Yueh Li, Pei-Ching Yeh, Chih-Jen Lin