Abstract: Systems and methods for optimizing data flow in an integrated circuit includes creating a task graph based on transforming an optimized network graph for a neural network application, wherein creating the task graph includes: enumerating a plurality of distinct tasks based on a decomposition of each of a plurality of network operations of the optimized network graph; and allocating a data buffer to each of pairs of dependent tasks of the plurality of distinct tasks based on the decomposition of each of the plurality of network operations of the optimized network graph; encoding a token-informed task scheduler based on a composition of the task graph, wherein the encoding the token-informed task scheduler includes: programming the token-informed task scheduler to cause an execution of the plurality of distinct tasks based on identifying a state of a respective data buffer between each of the pairs of dependent tasks.

Abstract: Systems and methods for optimizing data flow in an integrated circuit includes creating a task graph based on transforming an optimized network graph for a neural network application, wherein creating the task graph includes: enumerating a plurality of distinct tasks based on a decomposition of each of a plurality of network operations of the optimized network graph; and allocating a data buffer to each of pairs of dependent tasks of the plurality of distinct tasks based on the decomposition of each of the plurality of network operations of the optimized network graph; encoding a token-informed task scheduler based on a composition of the task graph, wherein the encoding the token-informed task scheduler includes: programming the token-informed task scheduler to cause an execution of the plurality of distinct tasks based on identifying a state of a respective data buffer between each of the pairs of dependent tasks.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods for optimizing data flow in an integrated circuit includes creating a task graph based on transforming an optimized network graph for a neural network application, wherein creating the task graph includes: enumerating a plurality of distinct tasks based on a decomposition of each of a plurality of network operations of the optimized network graph; and allocating a data buffer to each of pairs of dependent tasks of the plurality of distinct tasks based on the decomposition of each of the plurality of network operations of the optimized network graph; encoding a token-informed task scheduler based on a composition of the task graph, wherein the encoding the token-informed task scheduler includes: programming the token-informed task scheduler to cause an execution of the plurality of distinct tasks based on identifying a state of a respective data buffer between each of the pairs of dependent tasks.

Abstract: Systems and methods for improving a computational performance of a mixed-signal integrated circuit includes identifying a suboptimal graph component of a computation graph of a subject application, wherein: (i) the computation graph comprises a plurality of graphical nodes representing computational operations and a plurality of graphical edges representing data dependencies between the graphical nodes, and (ii) the suboptimal graph component comprises a subset of the plurality of graphical nodes and the plurality of graphical edges that do not satisfy an optimal operation threshold; at compile time, selectively applying an optimizing transformation to the suboptimal graph component based on attributes of a first activation function within the suboptimal graph component, wherein the optimization transformation, when applied, transforms the suboptimal graph component to an optimal graph component that satisfies the optimal operation threshold; and reconstructing the computation graph using the optimal graph co

Abstract: Systems and methods for optimizing data flow in an integrated circuit includes creating a task graph based on transforming an optimized network graph for a neural network application, wherein creating the task graph includes: enumerating a plurality of distinct tasks based on a decomposition of each of a plurality of network operations of the optimized network graph; and allocating a data buffer to each of pairs of dependent tasks of the plurality of distinct tasks based on the decomposition of each of the plurality of network operations of the optimized network graph; encoding a token-informed task scheduler based on a composition of the task graph, wherein the encoding the token-informed task scheduler includes: programming the token-informed task scheduler to cause an execution of the plurality of distinct tasks based on identifying a state of a respective data buffer between each of the pairs of dependent tasks.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods for improving a computational performance of a mixed-signal integrated circuit includes identifying a suboptimal graph component of a computation graph of a subject application, wherein: (i) the computation graph comprises a plurality of graphical nodes representing computational operations and a plurality of graphical edges representing data dependencies between the graphical nodes, and (ii) the suboptimal graph component comprises a subset of the plurality of graphical nodes and the plurality of graphical edges that do not satisfy an optimal operation threshold; at compile time, selectively applying an optimizing transformation to the suboptimal graph component based on attributes of a first activation function within the suboptimal graph component, wherein the optimization transformation, when applied, transforms the suboptimal graph component to an optimal graph component that satisfies the optimal operation threshold; and reconstructing the computation graph using the optimal graph co

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.