Patents by Inventor Pei-En Chang
Pei-En Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978385Abstract: This disclosure provides various techniques for providing fine-grain digital and analog pixel compensation to account for voltage error across an electronic display. By employing a two-dimensional digital compensation and a local analog compensation, a fine-grain and robust pixel compensation scheme may be provided to the electronic display.Type: GrantFiled: August 16, 2022Date of Patent: May 7, 2024Assignee: Apple Inc.Inventors: Yao Shi, Wei H Yao, Hyunwoo Nho, Jie Won Ryu, Kingsuk Brahma, Li-Xuan Chuo, Hyunsoo Kim, Myungjoon Choi, Ce Zhang, Alex H Pai, Shengkui Gao, Rungrot Kitsomboonloha, Shatam Agarwal, Vehbi Calayir, Chaohao Wang, Steven N Hanna, Pei-En Chang
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Publication number: 20240086014Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The shielding layers may include shielding structures such as a conductive mesh structure and/or a transparent conductive film. The shielding structures may be actively driven or passively biased. In the active driving scheme, one or more inverting circuits may receive a noise signal from a cathode layer in the display and/or from the shielding structures, invert the received noise signal, and drive the inverted noise signal back onto the shielding structures to prevent any noise from the display from negatively impacting the performance of the touch sensors. In the passive biasing scheme, the shielding structures may be biased to a power supply voltage.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Rungrot Kitsomboonloha, Donggeon Han, Jason N Gomez, Kyung Wook Kim, Nikolaus Hammler, Pei-En Chang, Saman Saeedi, Shih Chang Chang, Shinya Ono, Suk Won Hong, Szu-Hsien Lee, Victor H Yin, Young-Jik Jo, Yu-Heng Cheng, Joyan G Sanctis, Hongwoo Lee
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Patent number: 11922887Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The diode may be coupled to drive transistor circuitry, a data loading transistor, and emission transistors. The drive transistor circuitry may include at least two transistor portions connected in series. The data loading transistor has a drain region connected to a data line and a source region connected directly to the drive transistor circuitry. The data line may be connected to and overlap the drain region of the data loading transistor. The data line and the source region of the data loading transistor are non-overlapping to reduce row-to-row crosstalk.Type: GrantFiled: July 6, 2021Date of Patent: March 5, 2024Assignee: Apple Inc.Inventors: Shinya Ono, Chin-Wei Lin, Chuan-Jung Lin, Gihoon Choo, Hassan Edrees, Hei Kam, Jung Yen Huang, Pei-En Chang, Rungrot Kitsomboonloha, Szu-Hsien Lee, Zino Lee
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Patent number: 11861110Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The shielding layers may include shielding structures such as a conductive mesh structure and/or a transparent conductive film. The shielding structures may be actively driven or passively biased. In the active driving scheme, one or more inverting circuits may receive a noise signal from a cathode layer in the display and/or from the shielding structures, invert the received noise signal, and drive the inverted noise signal back onto the shielding structures to prevent any noise from the display from negatively impacting the performance of the touch sensors. In the passive biasing scheme, the shielding structures may be biased to a power supply voltage.Type: GrantFiled: September 29, 2022Date of Patent: January 2, 2024Assignee: Apple Inc.Inventors: Rungrot Kitsomboonloha, Donggeon Han, Jason N Gomez, Kyung Wook Kim, Nikolaus Hammler, Pei-En Chang, Saman Saeedi, Shih Chang Chang, Shinya Ono, Suk Won Hong, Szu-Hsien Lee, Victor H Yin, Young-Jik Jo, Yu-Heng Cheng, Joyan G Sanctis, Hongwoo Lee
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Publication number: 20230089942Abstract: This disclosure provides various techniques for providing fine-grain digital and analog pixel compensation to account for voltage error across an electronic display. By employing a two-dimensional digital compensation and a local analog compensation, a fine-grain and robust pixel compensation scheme may be provided to the electronic display.Type: ApplicationFiled: August 16, 2022Publication date: March 23, 2023Inventors: Yao Shi, Wei H Yao, Hyunwoo Nho, Jie Won Ryu, Kingsuk Brahma, Li-Xuan Chuo, Hyunsoo Kim, Myungjoon Choi, Ce Zhang, Alex H Pai, Shengkui Gao, Rungrot Kitsomboonloha, Shatam Agarwal, Vehbi Calayir, Chaohao Wang, Steven N Hanna, Pei-En Chang
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Publication number: 20230084423Abstract: Embodiments presented herein relate to reducing visual artifacts on an electronic display caused by an intra-frame pause. To do so, the intra-frame pause may be divided into smaller intra-frame pause segments. The intra-frame pause segments may be applied to the display during different image frames and/or at different locations on the electronic display. For example, each intra-frame pause segment may be applied to a different location on the electronic display. In some embodiments, multiple intra-frame pause segments may be applied during a single image frame. In some embodiments, the intra-frame pause segments may be applied to various image frames and at various location on the electronic display according to a pattern. To reduce band flickering that may be caused by the different locations of the intra-frame pause segments, an emission duty of one or more rows of pixels of the display may be adjusted.Type: ApplicationFiled: June 29, 2022Publication date: March 16, 2023Inventors: Myungjoon Choi, Jie Won Ryu, Hyunwoo Nho, Xiaokai Li, Kaikai Guo, Szu-Hsien Lee, Rungrot Kitsomboonloha, Pei-En Chang, Amit Nayyar, Vehbi Calayir
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Patent number: 11605330Abstract: Embodiments presented herein relate to reducing visual artifacts on an electronic display caused by an intra-frame pause. To do so, the intra-frame pause may be divided into smaller intra-frame pause segments. The intra-frame pause segments may be applied to the display during different image frames and/or at different locations on the electronic display. For example, each intra-frame pause segment may be applied to a different location on the electronic display. In some embodiments, multiple intra-frame pause segments may be applied during a single image frame. In some embodiments, the intra-frame pause segments may be applied to various image frames and at various location on the electronic display according to a pattern. To reduce band flickering that may be caused by the different locations of the intra-frame pause segments, an emission duty of one or more rows of pixels of the display may be adjusted.Type: GrantFiled: June 29, 2022Date of Patent: March 14, 2023Assignee: Apple Inc.Inventors: Myungjoon Choi, Jie Won Ryu, Hyunwoo Nho, Xiaokai Li, Kaikai Guo, Szu-Hsien Lee, Rungrot Kitsomboonloha, Pei-En Chang, Amit Nayyar, Vehbi Calayir
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Patent number: 11580905Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.Type: GrantFiled: May 19, 2022Date of Patent: February 14, 2023Assignee: Apple Inc.Inventors: Rungrot Kitsomboonloha, Chin-Wei Lin, Shinya Ono, Gihoon Choo, Hao-Lin Chiu, Kyung Wook Kim, Pei-En Chang, Szu-Hsien Lee, Zino Lee
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Publication number: 20230014107Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.Type: ApplicationFiled: May 19, 2022Publication date: January 19, 2023Inventors: Rungrot Kitsomboonloha, Chin-Wei Lin, Shinya Ono, Gihoon Choo, Hao-Lin Chiu, Kyung Wook Kim, Pei-En Chang, Szu-Hsien Lee, Zino Lee
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Patent number: 11462608Abstract: An electronic device may include a display with pixels formed using light-emitting diodes, thin-film silicon transistors, thin-film semiconducting-oxide transistors, and capacitors. The silicon transistors, semiconducting-transistors, and capacitors may have control terminals that are coupled to gate or routing lines that extend across the face of the display and that are formed in a low resistance source-drain metal routing layer. Forming routing/gate lines using the low resistance source-drain metal routing layer dramatically reduces the resistance of the gate lines, which enables better timing margins for large display panels operating at higher refresh rates.Type: GrantFiled: January 7, 2021Date of Patent: October 4, 2022Assignee: Apple Inc.Inventors: Shinya Ono, Chin-Wei Lin, Akira Matsudaira, Jiun-Jye Chang, Jung Yen Huang, Pei-En Chang, Rungrot Kitsomboonloha, Szu-Hsien Lee
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Publication number: 20210305353Abstract: An electronic device may include a display with pixels formed using light-emitting diodes, thin-film silicon transistors, thin-film semiconducting-oxide transistors, and capacitors. The silicon transistors, semiconducting-transistors, and capacitors may have control terminals that are coupled to gate or routing lines that extend across the face of the display and that are formed in a low resistance source-drain metal routing layer. Forming routing/gate lines using the low resistance source-drain metal routing layer dramatically reduces the resistance of the gate lines, which enables better timing margins for large display panels operating at higher refresh rates.Type: ApplicationFiled: January 7, 2021Publication date: September 30, 2021Inventors: Shinya Ono, Chin-Wei Lin, Akira Matsudaira, Jiun-Jye Chang, Jung Yen Huang, Pei-En Chang, Rungrot Kitsomboonloha, Szu-Hsien Lee
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Patent number: 10409118Abstract: An electronic device may have a housing and a display in the housing. The display may have one or more curved edges such as curved edges associated with rounded corners in the display and housing. The display may have an array of pixels. The display may include full-strength pixels and may have a band of antialiasing pixels having selectively reduced strengths to visually smooth content displayed along the curved edges. The pixels may be organic light-emitting diode pixels, liquid crystal display pixels, or other display pixels. Organic light-emitting diode pixels may have drive transistors and associated organic light-emitting diodes. Selectively elevated series or opaque light blocking structures of selectively reduced areas may be used to selectively reduce the strength of the antialiasing pixels. Liquid crystal display pixels may include electrodes of different shapes and/or opaque layer openings of different sizes to form antialiasing pixels in desired patterns.Type: GrantFiled: April 26, 2017Date of Patent: September 10, 2019Assignee: Apple Inc.Inventors: Pei-En Chang, Szu-Hsien Lee, Hsin-Ying Chiu, Chun-Yao Huang, Kyung Wook Kim, Shih Chang Chang, Hossein Nemati
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Patent number: 10354607Abstract: A display may have an array of pixels. Rows of pixels may receive gate line signals over gate lines. Display driver circuitry may have an adjustable clock generator that generates a series of clock pulses with different respective fall times to help equalize kickback voltages in the pixels of different rows. Within each row, gate lines may be provided with multiple parallel lines shorted at a series of tap points to help equalize kickback voltages across the pixels of different columns. A clock path may be formed between the clock generator and gate driver circuits. The clock path may run along an edge of the array of pixels. To help equalize kickback voltages in the pixels of different rows, the clock path may have first and second parallel metal lines that are selectively shorted to each other at a series of tap point locations along the clock path.Type: GrantFiled: August 23, 2017Date of Patent: July 16, 2019Assignee: Apple Inc.Inventors: Kwang Soon Park, Pei-En Chang, Szu-Hsien Lee
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Patent number: 10303013Abstract: An electronic device may have a housing and a display in the housing. The display may have one or more curved edges such as curved edges associated with rounded corners in the display and housing. The display may have an array of pixels. The display may include full-strength pixels and may have a band of antialiasing pixels having selectively reduced strengths to visually smooth content displayed along the curved edges. The antialiasing pixels may include single-opening pixels that each have a single opaque masking layer opening and may include dual-opening pixels that each include a pair of opaque masking layer openings. The single-opening pixels may be stronger than the dual-opening pixels.Type: GrantFiled: April 30, 2018Date of Patent: May 28, 2019Assignee: Apple Inc.Inventors: Hossein Nemati, Pei-En Chang, Yuan Chen, Tae Woon Cha, Sung H. Kim, Chia Hsuan Tai
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Publication number: 20180308445Abstract: A display may have an array of pixels. Rows of pixels may receive gate line signals over gate lines. Display driver circuitry may have an adjustable clock generator that generates a series of clock pulses with different respective fall times to help equalize kickback voltages in the pixels of different rows. Within each row, gate lines may be provided with multiple parallel lines shorted at a series of tap points to help equalize kickback voltages across the pixels of different columns. A clock path may be formed between the clock generator and gate driver circuits. The clock path may run along an edge of the array of pixels. To help equalize kickback voltages in the pixels of different rows, the clock path may have first and second parallel metal lines that are selectively shorted to each other at a series of tap point locations along the clock path.Type: ApplicationFiled: August 23, 2017Publication date: October 25, 2018Inventors: Kwang Soon Park, Pei-En Chang, Szu-Hsien Lee
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Publication number: 20180246363Abstract: An electronic device may have a housing and a display in the housing. The display may have one or more curved edges such as curved edges associated with rounded corners in the display and housing. The display may have an array of pixels. The display may include full-strength pixels and may have a band of antialiasing pixels having selectively reduced strengths to visually smooth content displayed along the curved edges. The antialiasing pixels may include single-opening pixels that each have a single opaque masking layer opening and may include dual-opening pixels that each include a pair of opaque masking layer openings. The single-opening pixels may be stronger than the dual-opening pixels.Type: ApplicationFiled: April 30, 2018Publication date: August 30, 2018Inventors: Hossein Nemati, Pei-En Chang, Yuan Chen, Tae Woon Cha, Sung H. Kim, Chia Hsuan Tai
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Patent number: 8242527Abstract: A light emitting device for generating infrared light includes a substrate, a first metal layer, a dielectric layer and a second metal layer. The substrate has a first surface. The first metal layer is formed on the first surface of the substrate. The dielectric layer is formed on the first metal layer. A thickness of the dielectric layer is greater than a particular value. The second metal layer is formed on the dielectric layer. When the light emitting device is heated, the dielectric layer has a waveguide mode such that the infrared light generated by the light emitting device can be transmitted in the dielectric layer. A wavelength of the infrared light generated in the waveguide mode relates to the thickness of the dielectric layer.Type: GrantFiled: March 22, 2010Date of Patent: August 14, 2012Assignee: National Taiwan UniversityInventors: Si-Chen Lee, Yu-Wei Jiang, Yi-Ting Wu, Ming-Wei Tsai, Pei-En Chang
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Publication number: 20100213492Abstract: A light emitting device for generating infrared light includes a substrate, a first metal layer, a dielectric layer and a second metal layer. The substrate has a first surface. The first metal layer is formed on the first surface of the substrate. The dielectric layer is formed on the first metal layer. A thickness of the dielectric layer is greater than a particular value. The second metal layer is formed on the dielectric layer. When the light emitting device is heated, the dielectric layer has a waveguide mode such that the infrared light generated by the light emitting device can be transmitted in the dielectric layer. A wavelength of the infrared light generated in the waveguide mode relates to the thickness of the dielectric layer.Type: ApplicationFiled: March 22, 2010Publication date: August 26, 2010Applicant: NATIONAL TAIWAN UNIVERSITYInventors: Si-Chen Lee, Yu-Wei Jiang, Yi-Ting Wu, Ming-Wei Tsai, Pei-En Chang