Patents by Inventor Pei Fan Tong

Pei Fan Tong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170062311
    Abstract: A packaged IC device has a power bar assembly with one or more power distribution bars, mounted on top of the IC die, which enables assembly using a lead frame that does not include any power distribution bars. External power supply voltages are brought to the IC die by (i) a corresponding first bond wire that connects a lead frame lead to a corresponding die-mounted power distribution bar and (ii) a corresponding second bond wire that connects the power distribution bar to a corresponding bond pad on the IC die. As such, different types of packaged IC devices having different numbers and/or configurations of power distribution bars can be assembled using a single, generic lead frame design having a die pad, tie bars, and leads, but no power distribution bars.
    Type: Application
    Filed: August 24, 2015
    Publication date: March 2, 2017
    Inventors: Chee Seng Foong, Yin Kheng Au, Ly Hoon Khoo, Wen Shi Koh, Pei Fan Tong
  • Publication number: 20160071789
    Abstract: A method for forming a pass-through layer of an interposer of a packaged semiconductor device in which conducting structures are extended between first and second ends of a casing. The conducting structures are subsequently encapsulated in a molding compound to form a molded bar, and the molded bar is sliced to obtain the pass-through layer. The pass-through layer has conducting vias, each corresponding to a sliced section of one of the conducting structures. The cost of pass-through layers formed in this manner may be less than that of comparable silicon or glass pass-through layers.
    Type: Application
    Filed: September 8, 2014
    Publication date: March 10, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Pei Fan Tong, Boon Yew Low, Lan Chu Tan
  • Patent number: 9196578
    Abstract: A semiconductor package has multiple dies and an interior power bar that extends within an interior space formed within the die flag between the dies. The bond pads located on the interior side of each die are wire-bonded to the interior power bar. Some embodiments may have more than two dies and/or more than one interior power bar between each pair of adjacent dies.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: November 24, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Sheau Mei Lim, Meng Kong Lye, Pei Fan Tong