Patents by Inventor PEI HSIEH
PEI HSIEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145653Abstract: A manufacturing method of a display device includes forming light emitting components on a first substrate, the light emitting components include a first side and a second side, and the second side is away from the first substrate; forming a circuit layer on the first substrate and on the second side of the light emitting components; forming a first protective layer on the circuit layer and forming an insulating layer on the first protective layer; removing the first substrate after forming a second substrate on the insulating layer; forming a black matrix layer on the first side of the light emitting components, and the black matrix layer includes openings; forming light conversion layers in the openings of the black matrix layer; forming a second protective layer on the black matrix layer and the light conversion layers; and forming a third substrate on the second protective layer.Type: ApplicationFiled: May 12, 2023Publication date: May 2, 2024Applicant: HANNSTAR DISPLAY CORPORATIONInventors: Chun-I Chu, Yu-Chi Chiao, Yung-Li Huang, Hung-Ming Chang, Cheng-Yu Lin, Huan-Hsun Hsieh, CHeng-Pei Huang
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Publication number: 20240128009Abstract: A magnetic device includes a magnetic core and at least two windings. The magnetic core includes an annular main body and a hollow portion. Each of the at least two windings includes a coil with a plurality of turns. Each turn of the coil penetrates through the hollow portion and is disposed around the annular main body. The at least two windings are disposed around the annular main body to form at least three winding regions. Each of the winding regions except a winding region which is last formed has at least three winding layers stacked up one by one. The number of the winding layers of the winding regions except the winding region which is last formed is odd and greater than or equal to three.Type: ApplicationFiled: January 12, 2023Publication date: April 18, 2024Inventors: Meng-Chen Hsieh, Chun-Ching Yen, Huai-Pei Tung
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Publication number: 20230351283Abstract: In an approach for optimizing project and team success, prior to a user initiating a project, a processor creates a digital profile. A processor sets up the digital profile with a set of data gathered from one or more project related documents for a set of previous projects of the user. Responsive to the user initiating the project, a processor identifies one or more documents related to the project. A processor analyzes the one or more documents related to the project. A processor predicts an outcome of the project using machine learning, wherein the outcome of the project is a set of measures indicating a success factor, a quality factor, and a risk factor of the project. A processor generates an optimization suggestion, wherein the optimization suggestion is a suggestion to adjust one or more parameters of the project. A processor outputs the optimization suggestion to the user.Type: ApplicationFiled: April 28, 2022Publication date: November 2, 2023Inventors: PEI HSIEH, Steve Rechtman, Christopher F. Ackermann, Jennifer M. Hatfield, Jeremy R. Fox, Lucia Larise Stavarache, XINDELING PAN
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THERMOPLASTIC COMPOSITION, THERMOPLASTIC COMPOSITE, AND METHOD FOR PRODUCING THERMOPLASTIC COMPOSITE
Publication number: 20230174784Abstract: The present invention relates to a thermoplastic composition, a thermoplastic composite, and a method for producing the thermoplastic composite. In the method for producing the thermoplastic composite, a polymer, an acid-modified lignin with a specific element content and a compatibilizer with a specific melt flow index and a specific maleic anhydride content are used to produce the thermoplastic composite. Hydroxy groups of the acid-modified lignin react with maleic anhydride groups of the compatibilizer to generate ester bonds via an in-situ reaction catalyzed by acidic groups of the acid-modified lignin to enhance compatibility between the polymer and the lignin, thereby increasing a mechanical strength of the resulted thermoplastic composite.Type: ApplicationFiled: November 29, 2022Publication date: June 8, 2023Inventors: Kwang-Ming CHEN, Jung-Hung KAO, Kun-Pei HSIEH, Chao-Shun CHANG, Yen-Ting LIN, Hung-Jue SUE -
Publication number: 20230060956Abstract: A method of forming a semiconductor device structure includes forming a resist structure over a substrate, the resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer, wherein the hydrogen plasma treatment is configured to smooth sidewalls of the trench, and the hydrogen plasma treatment is performed at a temperature ranging from about 200° C. to about 600° C. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.Type: ApplicationFiled: November 10, 2022Publication date: March 2, 2023Inventors: Sheng-Lin HSIEH, I-Chih CHEN, Ching-Pei HSIEH, Kuan Jung CHEN
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Patent number: 11527406Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a resist structure over a substrate. The resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer. The hydrogen plasma treatment is configured to smooth sidewalls of the trench without etching the ARC layer. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.Type: GrantFiled: January 14, 2020Date of Patent: December 13, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITEDInventors: Sheng-Lin Hsieh, I-Chih Chen, Ching-Pei Hsieh, Kuan Jung Chen
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Publication number: 20220204661Abstract: The present application relates to a polypropylene with high melt flow index and a method for producing the same, and meltblown fiber fabrics. A reacting mixture is firstly provided, and a polymerization process is performed to the reacting mixture in a slurry reaction system to obtain the polypropylene. The reacting mixture includes propylene monomers, Ziegler-Natta catalysts, organoaluminum compounds and electron donor. The polypropylene has high melt flow index and adjustable melting point and molecular weight distribution, such that it is used to produce the meltblown fiber fabrics.Type: ApplicationFiled: October 18, 2021Publication date: June 30, 2022Inventors: Kwang-Ming CHEN, Kun-Pei HSIEH, Jung-Hung KAO, Chao-Shun CHANG, Hsing-Chun CHEN
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Publication number: 20210388180Abstract: The present disclosure provides a copper nanowire composition. The a copper nanowire composition includes copper nanowire having associated alkylamine ligands with the structure HNR1R2. where R1 and R2 are independently hydrogen, alkyl or arylalkyl groups. The copper nanowire has an aspect ratio of at least 10. The associated alkylamine ligand is NR1R2 which contains at least 12 carbon atoms.Type: ApplicationFiled: June 15, 2021Publication date: December 16, 2021Inventors: Hung-Jue SUE, Chia-Ying TSAI, Kwang-Ming CHEN, Kun-Pei HSIEH, Chao-Shun CHANG, Ssu-Ping HUANG
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Patent number: 11158608Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first redistribution structure, a second redistribution structure, a first semiconductor die, a second semiconductor die and an encapsulant. The second redistribution structure is vertically overlapped with the first redistribution structure. The first and second semiconductor dies are located between the first and second redistribution structures, and respectively have an active side and a back side opposite to the active side, as well as a conductive pillar at the active side. The back side of the first semiconductor die is attached to the back side of the second semiconductor die. The conductive pillar of the first semiconductor die is attached to the first redistribution structure, whereas the conductive pillar of the second semiconductor die extends to the second redistribution structure.Type: GrantFiled: September 25, 2019Date of Patent: October 26, 2021Assignee: Powertech Technology Inc.Inventors: Kuang-Jen Shen, Chen-Pei Hsieh
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Publication number: 20210183644Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a resist structure over a substrate. The resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer. The hydrogen plasma treatment is configured to smooth sidewalls of the trench without etching the ARC layer. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.Type: ApplicationFiled: January 14, 2020Publication date: June 17, 2021Inventors: Sheng-Lin HSIEH, I-Chih CHEN, Ching-Pei HSIEH, Kuan Jung CHEN
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Patent number: 11018299Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.Type: GrantFiled: December 13, 2019Date of Patent: May 25, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Fu-Ting Sung, Shih-Chang Liu
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Publication number: 20210091043Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first redistribution structure, a second redistribution structure, a first semiconductor die, a second semiconductor die and an encapsulant. The second redistribution structure is vertically overlapped with the first redistribution structure. The first and second semiconductor dies are located between the first and second redistribution structures, and respectively have an active side and a back side opposite to the active side, as well as a conductive pillar at the active side. The back side of the first semiconductor die is attached to the back side of the second semiconductor die. The conductive pillar of the first semiconductor die is attached to the first redistribution structure, whereas the conductive pillar of the second semiconductor die extends to the second redistribution structure.Type: ApplicationFiled: September 25, 2019Publication date: March 25, 2021Applicant: Powertech Technology Inc.Inventors: Kuang-Jen Shen, Chen-Pei Hsieh
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Patent number: 10957852Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.Type: GrantFiled: April 20, 2020Date of Patent: March 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu-Ting Sung, Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Shih-Chang Liu
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Publication number: 20200251653Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.Type: ApplicationFiled: April 20, 2020Publication date: August 6, 2020Inventors: Fu-Ting Sung, Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Shih-Chang Liu
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Patent number: 10629811Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.Type: GrantFiled: December 18, 2018Date of Patent: April 21, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Ting Sung, Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Shih-Chang Liu
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Publication number: 20200119272Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.Type: ApplicationFiled: December 13, 2019Publication date: April 16, 2020Inventors: Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Fu-Ting Sung, Shih-Chang Liu
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Patent number: 10516107Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.Type: GrantFiled: December 12, 2018Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Fu-Ting Sung, Shih-Chang Liu
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Patent number: 10483322Abstract: A memory device includes a first inter-layer dielectric layer, plural conductive features, plural memory structures, a filler, and a second inter-layer dielectric layer. The conductive features are embedded in the first inter-layer dielectric layer. The memory structures are respectively over the conductive features. The filler is in between the memory structures. The second inter-layer dielectric layer is over the filler and the memory structures, and the second inter-layer dielectric layer and the filler form an interface, in which the interface extends from one of the memory structures to another of the memory structures.Type: GrantFiled: June 8, 2017Date of Patent: November 19, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ching-Pei Hsieh, Hsia-Wei Chen, Yu-Wen Liao
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Publication number: 20190148638Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.Type: ApplicationFiled: December 18, 2018Publication date: May 16, 2019Inventors: Fu-Ting Sung, Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Shih-Chang Liu
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Publication number: 20190115531Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.Type: ApplicationFiled: December 12, 2018Publication date: April 18, 2019Inventors: Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Fu-Ting Sung, Shih-Chang Liu