Abstract: A SAR ADC includes: a sample-hold (S/H) circuit sampling an input voltage to generate a S/H output signal; a DAC generating a DAC output signal; a comparator comparing the DAC output signal with the S/H output signal to generate a comparison output signal; a SAR combinational digital circuit group; a multiplexer circuit; and a plurality of registers for registering the comparison output signal as register output signals and outputting as an output signal of the SAR ADC. The SAR combinational digital circuit group generates a plurality of first and second SAR output signals based on the register output signals. The multiplexer circuit is controlled by on the register output signals to select among the first and the second SAR output signals as a plurality of multiplexer output signals for sending to the DAC. A capacitor coupling relationship of the DAC is controlled by the multiplexer output signals.

Abstract: A digital compute-in-memory (DCIM) macro includes a memory cell array and an arithmetic logic unit (ALU). The memory cell array stores weight data of a neural network. The ALU receives parallel bits of a same input channel in an activation input, and generates a convolution computation output of the parallel bits and target weight data in the memory cell array.

Abstract: According to an aspect of the disclosure, the disclosure provides an ADC which includes not limited to: a DAC configured to generate a positive input delta voltage and a negative input delta voltage, a comparator electrically connected to the DAC and configured to receive the positive input delta voltage to generate a first digital output value and to receive the negative input delta voltage to generate a second digital output value, a logic circuit configured to receive, from the comparator, the first digital output value and the second digital output value to generate a digital quantization code according to half of a sum of the first digital output value and the second digital output value, and a calibration circuit configured to receive the digital quantization code from the logic circuit and calibrate an output of the ADC according to the digital quantization code to eliminate an offset error value.

Abstract: A digital compute-in-memory (DCIM) system includes a first DCIM macro. The first DCIM macro includes a first memory cell array and a first arithmetic logic unit (ALU). The first memory cell array has N rows that are configured to store weight data of a neural network in a single weight data download session, wherein N is a positive integer not smaller than two. The first ALU is configured to receive a first activation input, and perform convolution operations upon the first activation input and a single row of weight data selected from the N rows of the first memory cell array to generate first convolution outputs.

Abstract: A controller includes a body and a surrounding part. The body has a control area for sending a control signal according to a movement of a thumb of a user. The surrounding part is connected to the body and used to surround and be fixed to a proximal phalange of an index finger of the user. The body is away from a joint between the proximal phalange and a metacarpal bone of the user.

Abstract: A system and method of adaptively testing a hearing function performs a hearing test including outputting a sound of a tested word chosen from a selected one of the word lists, receiving an input of a patient in response to the outputted sound, and determining whether the input matches with the tested word. The hearing test is repeated until a testing end condition is satisfied, wherein the selected one of the word lists in a next iteration of the hearing test has a next higher level of difficulty when the input matches with the tested word in a previous iteration of the hearing test, and the selected one of the word lists in the next iteration of the hearing test has a next lower level of difficulty when the input does not match with the tested word in the previous iteration of the hearing test.

Abstract: A dispatcher virtual assistant (DVA) that can augment the capability of emergency dispatchers while reducing human errors. Major functions of the DVA include updating an emergency incident's status in real time, recommending or reminding the dispatcher to take proper actions at the right timing, answering the dispatcher's inquiries for task-related information, and fulfilling the dispatcher's request for an incident report. The DVA system includes a dispatcher language model based on machine-learning and deep-learning algorithms, for extracting the status of a live incident from incoming incident logs, and for processing and answering inquiries or requests from the dispatcher. It is customizable for different types of emergencies and for different local communities. The DVA can be used in tandem with an existing CAD system.

Abstract: A dispatcher virtual assistant (DVA) that can augment the capability of emergency dispatchers while reducing human errors. Major functions of the DVA include updating an emergency incident's status in real time, recommending or reminding the dispatcher to take proper actions at the right timing, answering the dispatcher's inquiries for task-related information, and fulfilling the dispatcher's request for an incident report. The DVA system includes a dispatcher language model based on machine-learning and deep-learning algorithms, for extracting the status of a live incident from incoming incident logs, and for processing and answering inquiries or requests from the dispatcher. It is customizable for different types of emergencies and for different local communities. The DVA can be used in tandem with an existing CAD system.

Abstract: A tool manufacturing method includes the steps of preparing a cylindrical blank, dividing the blank into sections, changing an outer diameter of one of the sections, and shaping the sections to complete a tool. During the shaping step, the section whose outer diameter is changed is shaped into a symmetrical polygon for serving as a head portion of the tool and shaping another section to obtain a polygon with alternate concavities and convexities thereon for serving as an engaging portion of the tool. Accordingly, the progressive execution of the method prevents the deterioration of the blank made of a high carbon content metal material, allows the tool to keep good mechanical properties, increases the manufacturing efficiency, and reduces manufacturing costs.

Abstract: A tool manufacturing method includes the steps of preparing a cylindrical blank, dividing the blank into sections, changing an outer diameter of one of the sections, and shaping the sections to complete a tool. During the shaping step, the section whose outer diameter is changed is shaped into a symmetrical polygon for serving as a head portion of the tool and shaping another section to obtain a polygon with alternate concavities and convexities thereon for serving as an engaging portion of the tool. Accordingly, the progressive execution of the method prevents the deterioration of the blank made of a high carbon content metal material, allows the tool to keep good mechanical properties, increases the manufacturing efficiency, and reduces manufacturing costs.

Abstract: This invention provides programmable intelligent agents that facilitate and manage voice or video conversations between human users and chatbots over the Internet or the Public Switched Telephone Network. Functions of said intelligent agents include providing the communication connectivity, coordinating the human-chatbot conversation, reacting and responding to the human user's conversational behavior, and in certain applications, sending controlling signals to peripheral devices according to intents of the conversation, or receiving data from peripheral sensors as references to alter the course of the conversation. Furthermore, a said intelligent agent can serve as a user interface that enables human users in the vicinity of the intelligent agent to engage in an interactive three-way conversation with a chatbot and remote human users.

Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output to circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

Abstract: In one aspect, an LCD includes a display panel with a pixel matrix having M scan lines and N data lines, and a multiplexer feed-through compensation circuit, which includes P signal lines for providing P video signals, P multiplexers, and K pairs of control lines providing K pairs of control signals. Each multiplexer is electrically coupled to a corresponding signal line and has K channels. Each channel includes first and second switches parallel-connected between the signal line and a corresponding data line for selectively transmitting the video signal to the corresponding data line. Each pair of control lines is respectively electrically coupled to the first and second switches of a corresponding channel of each multiplexer. Each pair of control signals are configured such that a time turning off one of the first and second switches is earlier than that turning off the other switch.

Abstract: A six-coordinated ruthenium complex is represented by the following formula (I): RuL1L2L3??(I) wherein L1 represents a 2,2?-bipyridine-based bidentate ligand having at least two functional groups selected from COOH, a carboxylate group and the combination thereof; and L2 and L3 independently represent a 1-(haloalkylpyrazole)-isoquinoline-based bidentate ligand of formula (II) or formula (III).

Abstract: An active liquid crystal display panel includes a pixel array, a gate driving circuit, a data driving circuit, and an analog buffer. The gate driving circuit is used for driving M first scan lines where M is a natural number. The analog buffer is coupled to the gate driving circuit and includes M buffer circuits and a regulator. Each buffer circuit drives a corresponding second scan line according to an output signal of a corresponding first scan line of the M first scan lines, and the regulator is used for maintaining at least one reference voltage supplied to the M buffer circuits.

Abstract: In one aspect, an LCD includes a display panel with a pixel matrix having M scan lines and N data lines, and a multiplexer feed-through compensation circuit, which includes P signal lines for providing P video signals, P multiplexers, and K pairs of control lines providing K pairs of control signals. Each multiplexer is electrically coupled to a corresponding signal line and has K channels. Each channel includes first and second switches parallel-connected between the signal line and a corresponding data line for selectively transmitting the video signal to the corresponding data line. Each pair of control lines is respectively electrically coupled to the first and second switches of a corresponding channel of each multiplexer. Each pair of control signals are configured such that a time turning off one of the first and second switches is earlier than that turning off the other switch.

Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output to circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

Abstract: A multiplexer circuit includes multiple groups of switches and multiple groups of control lines. Each control line in each one of the groups of control lines is coupled to a control end of at least one switch in corresponding one of the groups of switches, and each group of control lines is configured for synchronously transmitting an identical group of control signals. A display panel and method for transmitting signals in a display panel is also disclosed herein.