Abstract: A method for encapsulating an integrated circuit chip is described. An intergrated circuit chip is attached to a substrate; a stress buffering material only covers corners of the integrated circuit chip; and an encapsulation material coats the integated circuit chip and a portion of the substrate.

Abstract: A method for encapsulating an integrated circuit chip is described. An integrated circuit chip is attached to a substrate. A dam is formed surrounding the integrated circuit chip. At least one corner of the integrated circuit chip is covered with a stress buffering material. The integrated circuit chip and all of the substrate within the dam are coated with an encapsulation material wherein the encapsulation material covers the stress buffering material and wherein the stress buffering material prevents delamination of the encapsulation material at the corners of the integrated circuit chip.

Abstract: A method for fabricating a wafer level chip scale package with discrete package encapsulation and devices formed by the method are described. A dry film photoresist layer is first deposited on top of a pre-processed wafer complete with a plurality of bond pads and an I/O redistribution metal layer. The dry film photoresist layer is then patterned to form a plurality of trench openings and a plurality of via openings followed by the process of depositing a liquid photoresist material into the plurality of trench openings and plating a conductive metal into the plurality of via openings to form via plugs. After the dry film photoresist layer is removed, an encapsulant layer is printed on top of the wafer to embed the protrusions formed by the liquid photoresist material and the via plugs.