Patents by Inventor Pei-Jan Wang

Pei-Jan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5963830
    Abstract: The present invention relates to a method of forming a barrier metal layer for a hot Al plug and its structure and more particularly to remarkably ameliorate the performance of a barrier metal layer preventing Al metal used as an interconnection layer from diffusing into a silicon substrate. A barrier metal layer according to the present invention is a stacked structure comprising a top layer of Tungsten (W) formed by a Chemical Vapor Deposition (CVD) method and a bottom layer of TiN. Then, a Al interconnection layer deposited at high temperature fills a plug and finishes a plug structure having advantages of low manufacturing cost and full prevention of Al diffusion.
    Type: Grant
    Filed: October 27, 1997
    Date of Patent: October 5, 1999
    Assignee: Mosel Vitelic Incorporated
    Inventors: Pei-Jan Wang, Yeong-Ruey Shiue, Yung-Tsun Lo, Hsien-Liang Meng
  • Patent number: 5776833
    Abstract: A method for forming a metal plug is provided. The method includes: a) forming a metal contact window in a substrate having an oxide layer; b) forming a barrier layer over a top surface of the oxide layer and a wall defining the metal contact window; c) forming a metal layer covering the barrier layer and filling up the metal contact window; d) removing a portion of the metal layer located above the barrier layer covering the top surface of the oxide layer by a chemical mechanical polishing method; and e) removing the barrier layer covering the top surface of the oxide layer by an etching method.
    Type: Grant
    Filed: September 4, 1996
    Date of Patent: July 7, 1998
    Assignee: Mosel Vitelic Inc.
    Inventors: Hsi-Chieh Chen, Champion Yi, Pei-Jan Wang, Yeong-Ruey Shiue
  • Patent number: 5770515
    Abstract: The present invention relates to a method of a sequencial WSi/.alpha.-Si sputtering process, more particularly to a method of in-situ wafer cooling for a sequencial WSi/.alpha.-Si sputtering process. A sputtering process of WSi and a sputtering process of .alpha.-Si are finished in a multi-chamber sputtering apparatus according to the invention; meanwhile, a wafer is cooled down by bolwing of inert gas before a process of sputtering .alpha.-Si starts. Thus, compared to traditional art of finishing WSi/.alpha.-Si sputtering in two apparatus, partial time of vacuuming and venting required in a sputtering process is saved according to the invention, thereby, shortening the production cycle time, reducing the possibility of wafer contamination, and suppressing the fabricating cost.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: June 23, 1998
    Assignee: Mosel Vitelic Incorporated
    Inventors: Hsien-Liang Meng, Elvis Huang, Pei-Jan Wang, Yeong Rvey Shiue
  • Patent number: 5670016
    Abstract: A method for cleaning a substrate prior to tungsten deposition is disclosed, said substrate having via holes and trenches lines thereon. The method includes steps ofproviding a solution of hydroxylamine sulfate; dipping said substrate in said solution; and agitating said solution by an agitating device.
    Type: Grant
    Filed: November 15, 1995
    Date of Patent: September 23, 1997
    Assignee: National Science Council
    Inventors: Mao-Chieh Chen, Wen-Kuan Yeh, Pei-Jan Wang, Lu-Min Liu
  • Patent number: 5629237
    Abstract: A method is described for forming tapered contact via holes in large scale integrated circuit structures which avoids the formation of a re-entrance profile. The re-entrance profile can form at the entrance to the contact via hole when a dry etch is used as a first etching step by redepositing material removed during the dry etch at the entrance of the contact via hole. This re-entrance profile makes the angle of entrance into the contact via hole greater than 90.degree. and the step coverage of metal filling the hole poor. This invention uses wet etching with a greater lateral etch rate than vertical etch rate as a first etching step in the formation of the contact via hole and avoids the formation of the re-entrance profile. The edges of the resulting contact via hole are smooth and the entrance angle into the contact via hole is substantially less than 90.degree.. The step coverage of metal later filling the contact via hole is substantially improved.
    Type: Grant
    Filed: October 19, 1995
    Date of Patent: May 13, 1997
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Pei-Jan Wang, Kuei-Lung Chou, Jiunn-Jyi Lin, Hsien-Wen Chang
  • Patent number: 5180689
    Abstract: A method is described for making a tapered opening for an integrated circuit having a feature size of about one micrometer or less which will in due course be filled with a metallurgy conductor. An integrated circuit structure is provided having device elements within a semiconductor substrate and multilayer insulating layers thereover. A resist masking layer is formed over the said multilayer insulating layer having openings therein in the areas where the said openings are desired. The multilayer insulating layer is anisotropically etched through a first thickness to form a first opening using the resist masking layer as a mask. A second thickness portion of the multilayer insulating layer is isotropically etched to substantially uniformly enlarge and taper the first opening while using the unchanged resist layer.
    Type: Grant
    Filed: September 10, 1991
    Date of Patent: January 19, 1993
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsien-Tsung Liu, Jin-Yuan Lee, Jiann-Kwang Wang, Chue-San Yoo, Pei-Jan Wang