Patents by Inventor Pei-Jen Wang

Pei-Jen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240152880
    Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.
    Type: Application
    Filed: February 13, 2023
    Publication date: May 9, 2024
    Applicant: OBOOK INC.
    Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chun-Jen Chen, Po-Hua Lin, Wei-Te Lin, Pei-Hsuan Weng, Mei-Su Wang, I-Cheng Lin, Cheng-Wei Chen
  • Patent number: 11955560
    Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Arnab Sen Gupta, Travis W. LaJoie, Sarah Atanasov, Chieh-Jen Ku, Bernhard Sell, Noriyuki Sato, Van Le, Matthew Metz, Hui Jae Yoo, Pei-Hua Wang
  • Patent number: 11929415
    Abstract: A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Chieh-Jen Ku, Pei-Hua Wang, Bernhard Sell, Travis W. Lajoie
  • Publication number: 20240065664
    Abstract: A physiological signal measurement device is disclosed. In some implementations, the physiological signal measurement device includes a fixing element, a rack, a first sensor, and a second sensor. The fixing element is configured to be fixed on a limb of a user. The rack is configured to engage the fixing element and includes a first end and a second end distal to the first end. The first sensor is disposed on the first end of the rack. The sensor is disposed on the second end of the rack. The first end of the rack has a first stiffness, the second end of the rack has a second stiffness, and the first stiffness is higher than the second stiffness.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Inventors: CHENG YAN GUO, KUAN JEN WANG, PEI-MING CHIEN, HAO-CHING CHANG
  • Publication number: 20230299124
    Abstract: A method of forming a capacitor is disclosed. The method includes forming a portion of a metallization layer on a substrate, forming a via layer on the substrate, and forming a first electrode between the metallization layer and the via layer, where the first electrode is electrically connected to the metallization layer. The method also includes forming a second electrode between the metallization layer and the via layer, where the second electrode is electrically connected to the via layer, and forming a dielectric layer between the first electrode and the second electrode, where the first electrode is not electrically connected to any other conductors other than through the metallization layer, and where the second electrode is not electrically connected to any conductors other than through the via layer.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 21, 2023
    Inventors: Pei-Jen Wang, Ching-Hung Kao, Tzy-Kuang Lee, Meng-Chang Ho, Kun-Mao Wu
  • Patent number: 11018362
    Abstract: Oxygen from water can be efficiently and economically achieved via water electrolysis on antimony, nickel doped tin oxide (Sb,Ni—SnO2/Ti) anode using low DC power. As O2 is evolved, it will be quickly reduced by adjacent cobalt oxide doped carbon nanofilm (Co3O4—CNF/Ti) to hydrogen peroxide (H2O2) and electricity. In the said electricity generation, O2 is first formed in O2 evolution reaction (OER), then, electricity is generated in O2 reduction reaction (ORR). Both of anode and cathode are shared by OER and ORR, yet, the former consumes energy and the latter yields electricity. It is the cathode, a load and the anode that form an electricity-forming circuit. The said circuit relies on clean water to supply the fuel, O2, hence, it is designated as all-water fuel cell (AWFC). Supercapacitor is employed as the load for AWFC, and onboard purifiers are providers of clean water for AWFC.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: May 25, 2021
    Inventors: Lih-Ren Shiue, Zhen-Hua Fei, Pei-Jen Wang
  • Publication number: 20200381758
    Abstract: Oxygen from water can be efficiently and economically achieved via water electrolysis on antimony, nickel doped tin oxide (Sb,Ni—SnO2/Ti) anode using low DC power. As O2 is evolved, it will be quickly reduced by adjacent cobalt oxide doped carbon nanofilm (Co3O4—CNF/Ti) to hydrogen peroxide (H2O2) and electricity. In the said electricity generation, O2 is first formed in O2 evolution reaction (OER), then, electricity is generated in O2 reduction reaction (ORR). Both of anode and cathode are shared by OER and ORR, yet, the former consumes energy and the latter yields electricity. It is the cathode, a load and the anode that form an electricity-forming circuit. The said circuit relies on clean water to supply the fuel, O2, hence, it is designated as all-water fuel cell (AWFC). Supercapacitor is employed as the load for AWFC, and onboard purifiers are providers of clean water for AWFC.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 3, 2020
    Inventors: Lih-Ren SHIUE, Zhen-Hua FEI, Pei-Jen WANG
  • Patent number: 8149513
    Abstract: The invention discloses a package structure of a liquid lens which includes a first substrate and an electrode on the first substrate. The package structure includes a second substrate, a first sleeve, a second sleeve, a first circular member, and a second circular member. The first substrate is fixed at the first sleeve to form a holding chamber for receiving a first dielectric liquid and a second dielectric liquid. The second substrate is disposed on the liquid lens and fixed at the second sleeve. The first sleeve is fixedly connected inside the first sleeve and the second substrate. The second circular member is disposed on the first circular member. The first and second circular member are located and urged between the first sleeve and the second sleeve to form a reserved expansion chamber.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: April 3, 2012
    Assignee: National Tsing Hua University
    Inventors: Pei-Jen Wang, Jer-Liang Andrew Yeh
  • Publication number: 20100079873
    Abstract: The invention discloses a package structure of a liquid lens which includes a first substrate and an electrode on the first substrate. The package structure includes a second substrate, a first sleeve, a second sleeve, a first circular member, and a second circular member. The first substrate is fixed at the first sleeve to form a holding chamber for receiving a first dielectric liquid and a second dielectric liquid. The second substrate is disposed on the liquid lens and fixed at the second sleeve. The first sleeve is fixedly connected inside the first sleeve and the second substrate. The second circular member is disposed on the first circular member. The first and second circular member are located and urged between the first sleeve and the second sleeve to form a reserved expansion chamber.
    Type: Application
    Filed: December 30, 2008
    Publication date: April 1, 2010
    Inventors: Pei-Jen Wang, Jer-Liang Andrew Yeh
  • Patent number: 6780761
    Abstract: The present invention pertains to a via-first dual damascene process. A semiconductor substrate having a conductive structure and a dielectric layer on the semiconductor substrate is provided. The dielectric layer has a via opening exposing the conductive structure. The via opening is filled with a gap-filling polymer to form a gap-filling polymer (GFP) layer on the dielectric layer. The GFP layer is etched back to a predetermined depth such that an exposed surface of the GFP layer is lower than surface of the dielectric layer to form a recess, thereby exposing portions of sidewalls of the via opening. A surface treatment for altering surface property of the sidewalls and the exposed surface of the GFP layer is then carried out, thereby preventing a subsequent deep UV photoresist from interacting with the sidewalls or the exposed surface of the GFP layer either in a chemical or physical way.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: August 24, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Ning Wu, Ming-Hsing Liu, Hsiao-Pang Chou, Ching-Piao Lin, Pei-Jen Wang
  • Patent number: 6600961
    Abstract: An intelligent control method for injection machine is to transplant the intelligent control and prediction techniques of a neural network to an injection machine, which has been exemplified capable of deciding the quasi best machine parameters rapidly in couple processing cycles for increasing yield with least loss, and for detecting and adjusting conditions until a desired operation environment is obtained.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: July 29, 2003
    Assignee: Mirle Automation Corporation
    Inventors: Jui-Ming Liang, Pei-Jen Wang
  • Patent number: 6500575
    Abstract: A method for fabricating cylindrical and prismatic rechargeable metal-air batteries is devised. The method includes using micro fans to control air flowing through the batteries via air pathways between the packs of electrodes and separator sheet. The air pathways are created by protrusions printed or molded on plastic spacer film. The air is used by the positive electrode for generating electricity when the metal-air battery is discharged. By conjunction of a second positive electrode and an energy storage device, the micro fans can be actuated as soon as the metal-air battery is demanded by a load. The in-cell air management can not only supply air for reactions but also shut the system to preserve materials when they are not in service.
    Type: Grant
    Filed: December 27, 1999
    Date of Patent: December 31, 2002
    Assignee: Industrial Technology Research Institute
    Inventors: Lih-Ren Shiue, Shinn-Horng Yeh, Wen-Jin Lee, Pei-Jen Wang, Chum-Sam Hong, Shu-Chin Chou, Horng-Jee Wang
  • Patent number: 6479307
    Abstract: A method of monitoring loss of silicon nitride, used to monitor the loss of a first etch stop layer below a first insulating layer in a first contact opening opening after the first contact opening is formed in the first insulating layer over a device region and scribe line of a wafer. A dummy wafer is provided on which stacks in sequence a second etch stop layer and a second insulating layer. The second insulating layer is patterned by removing a portion of the second insulating layer, so that a monitoring opening that exposes the second etch stop layer and a second contact opening are formed in the second insulating layer. A first measuring step is performed to measure a first thickness loss and a second thickness loss from the second etch stop layer exposed respectively by the monitoring opening and the second contact opening on the dummy wafer. And a correlation is established from the first and second thickness losses.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: November 12, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Shu-Ya Chuang, Gow-Wei Sun, Ga-Ming Hong, Steven Chen, Pei-Jen Wang
  • Publication number: 20020127746
    Abstract: A method of monitoring loss of silicon nitride, used to monitor the loss of a first etch stop layer below a first insulating layer in a first contact opening openingafter the first contact opening is formed in the first insulating layer over a device region and scribe line of a wafer. A dummy wafer is provided on which stacks in sequence a second etch stop layer and a second insulating layer. The second insulating layer is patterned by removing a portion of the second insulating layer, so that a monitoring opening that exposes the second etch stop layer and a second contact opening are formed in the second insulating layer. A first measuring step is performed to measure a first thickness loss and a second thickness loss from the second etch stop layer exposed respectively by the monitoring opening and the second contact opening on the dummy wafer. And a correlation is established from the first and second thickness losses.
    Type: Application
    Filed: May 10, 2001
    Publication date: September 12, 2002
    Inventors: Shu-Ya Chuang, Gow-Wei Sun, Ga-Ming Hong, Steven Chen, Pei-Jen Wang
  • Patent number: 6410422
    Abstract: A method of forming a local interconnect contact opening is described. A liner layer is formed on a substrate having a gate structure, a first source/drain region, and a second source/drain region formed thereon. A planarized dielectric layer is formed over the liner layer. A photoresist layer, which defines the location of the local interconnect contact opening, is formed over the dielectric layer. A one-step etching process is performed using a C5F8/CO/O2/Ar etching gas and the liner layer as an etching stop. The dielectric layer exposed by the opening of the photoresist layer is removed to expose the liner layer. The liner layer and the photoresist layer are removed.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: June 25, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Gow-Wei Sun, Pei-Jen Wang
  • Patent number: 6373152
    Abstract: An electricity storage device and a portable electric-powered tool. The device comprises at least a battery; at least a super capacitor, which has lower internal impedance, when fully charged, than that of the battery and connects the battery in parallel; and an output end for supplying the electricity. The super capacitor is the major power supply for the pulse current output; the battery is used for generating electricity to the super capacitor and is the secondary power supply for the pulse current output. The connection of the battery and the super capacitor does not need any converters or current-limiting resistors.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: April 16, 2002
    Assignee: Synergy Scientech Corp.
    Inventors: Pei-Jen Wang, Shun-Ming Huang, Wei-Chen Wu
  • Publication number: 20020019674
    Abstract: An intelligent control method for injection machine is to transplant the intelligent control and prediction techniques of a neural network to an injection machine, which has been exemplified capable of deciding the quasi best machine parameters rapidly in couple processing cycles for increasing yield with least loss, and for detecting and adjusting conditions until a desired operation environment is obtained.
    Type: Application
    Filed: December 29, 2000
    Publication date: February 14, 2002
    Inventors: Jui-Ming Liang, Pei-Jen Wang
  • Publication number: 20010051858
    Abstract: The present invention is to combine an experimental design method with a moldflow analysis software to simulate the real injection molding processes of the injection molding machine, analyze the simulation results, and develop a database for the quantitative relationship between the parameters of the injection molding machine and the parameters of the injection molding product quality. The database is then used to develop a neural network which can predict the qualities of the injection molding products. The operators of the injection molding machine can input the undetermined parameters to the developed neural network; after execution, the neural network outputs the predicted parameters of the injection molding product quality. The present invention can help the operators to set the parameters, cut down the time on finding appropriate molding parameters, reduce the time of futile try-and-error, and enhance quality by reducing defects.
    Type: Application
    Filed: December 15, 2000
    Publication date: December 13, 2001
    Inventors: Jui-Ming Liang, Pei-Jen Wang
  • Patent number: 6083825
    Abstract: An improved method of fabricating an unlanded via hole on a semiconductor substrate is provided. A conductive line and a patterned anti-reflection coating layer are sequentially formed on the substrate wherein the patterned anti-reflection coating layer has a smaller width than the conductive line and a portion of the conductive layer is exposed by the patterned anti-reflection coating layer. A planarized dielectric layer is formed over the substrate to cover the patterned anti-reflection coating layer and the conductive line. A via hole is formed in the planarized dielectric layer to expose portions of surface and sidewalls of the patterned anti-reflection coating layer as well as the conductive line.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: July 4, 2000
    Assignee: United Semiconductor Corp.
    Inventors: Jy-Hwang Lin, Yueh-Feng Ho, Pei-Jen Wang