Abstract: A filtering device, applicable in a transceiver, includes: a capacitive circuit coupled to an amplifying circuit by a first capacitive configuration or by a second capacitive configuration; and a resistive circuit coupled to the amplifying circuit by a first resistive configuration or by a second resistive configuration; wherein when the capacitive circuit is the first capacitive configuration, the filtering device is used to perform a first filtering process upon a receiving signal of the filtering device, and when the capacitive circuit is the second capacitive configuration, the filtering device is used to perform a second filtering process upon a transmitting signal of the filtering device.

Abstract: A filtering device, applicable in a transceiver, includes: a capacitive circuit coupled to an amplifying circuit by a first capacitive configuration or by a second capacitive configuration; and a resistive circuit coupled to the amplifying circuit by a first resistive configuration or by a second resistive configuration; wherein when the capacitive circuit is the first capacitive configuration, the filtering device is used to perform a first filtering process upon a receiving signal of the filtering device, and when the capacitive circuit is the second capacitive configuration, the filtering device is used to perform a second filtering process upon a transmitting signal of the filtering device.

Abstract: A receiving device includes a mixer, an AC coupling circuit, a post-stage circuit, and a DC offset calibration circuit. The mixer is utilized for mixing an input signal with a local oscillating (LO) signal from an oscillator to generate a converted signal. The AC coupling circuit is coupled to the mixer and utilized for reducing at least one portion of DC offset of the converted signal to generate a filtered signal. The post-stage circuit is coupled to the AC coupling circuit and utilized for processing the filtered signal to generate an output signal. The DC offset calibration circuit is coupled to the post-stage circuit and utilized for providing at least a compensation current for the post-stage circuit to reduce DC offset of the output signal.

Abstract: The invention provides an on-chip transformer balun formed among N successive isolating layers. The transformer includes a primary winding and a secondary winding. The primary winding includes a plurality of first semi-turn coils, a plurality of second semi-turn coils, a plurality of metal junctions, and a plurality of first metal bridges. The secondary winding includes a plurality of third semi-turn coils, a plurality of fourth semi-turn coils, and a plurality of second metal bridges. The first semi-turn coils are connected with the second semi-turn coils by the metal junctions and the first metal bridges. The third semi-turn coils are connected with the fourth semi-turn coils by the second metal bridges. By use of the multi-layer first metal bridges, the transformer according to the invention allows a larger input current than a conventional on-chip transformer.

Abstract: A receiving device includes a mixer, an AC coupling circuit, a post-stage circuit, and a DC offset calibration circuit. The mixer is utilized for mixing an input signal with a local oscillating (LO) signal from an oscillator to generate a converted signal. The AC coupling circuit is coupled to the mixer and utilized for reducing at least one portion of DC offset of the converted signal to generate a filtered signal. The post-stage circuit is coupled to the AC coupling circuit and utilized for processing the filtered signal to generate an output signal. The DC offset calibration circuit is coupled to the post-stage circuit and utilized for providing at least a compensation current for the post-stage circuit to reduce DC offset of the output signal.

Abstract: The invention provides an on-chip transformer balun formed among N successive isolating layers. The transformer includes a primary winding and a secondary winding. The primary winding includes a plurality of first semi-turn coils, a plurality of second semi-turn coils, a plurality of metal junctions, and a plurality of first metal bridges. The secondary winding includes a plurality of third semi-turn coils, a plurality of fourth semi-turn coils, and a plurality of second metal bridges. The first semi-turn coils are connected with the second semi-turn coils by the metal junctions and the first metal bridges. The third semi-turn coils are connected with the fourth semi-turn coils by the second metal bridges. By use of the multi-layer first metal bridges, the transformer according to the invention allows a larger input current than a conventional on-chip transformer.