Abstract: A printed circuit board comprising a differential microstrip pair including a neck-down area and an ultraviolet glue coating a portion of the neck-down area of the differential microstrip pair to control an impedance of the differential microstrip pair.

Abstract: A method for estimating performance values of chips includes: (A) using oscillation period vectors of a to-be-divide chip set to train a first neural network model to obtain a training error of the to-be-divided chip set, where in the first-time conducted step (A), the to-be-divided chip set includes the chips; (B) dividing the to-be-divided chip set into divided chip sets according to the training error; and (C) using oscillation period vectors of the divided chip sets as training data of a second neural network model, so that the second neural network model outputs weight vectors respectively corresponding to the divided chip sets. A product of oscillation period vector(s) of each divided chip set and a weight vector of the divided chip set is larger than a product of the oscillation period vector(s) of the divided chip set and a weight vector of each of rest of divided chip sets.

Abstract: A flying probe includes a test module and a processor. The test module measures a plurality of delta capacitances associated with a plurality of vias in a printed circuit board. The plurality of vias include first, second, third and fourth vias. Each different delta capacitance is measured between a different pair of the vias. The processor compares all the delta capacitances to a threshold value. In response to multiple delta capacitances associated with the first via being greater than or equal to the threshold value, the processor detects a possible via stripping issue for the first via.

Abstract: A temperature sensing device and a calibration method of the temperature sensing device are provided. Based on different conditions, the temperature sensing device generates a first digital sensing value and a second digital sensing value corresponding to an ambient temperature. The temperature sensing device generates a first sensing result value according to the first digital sensing value, a first compensation value, and a sensing difference value between the first digital sensing value and the second digital sensing value, and generates a second sensing result value according to the second digital sensing value, a second compensation value, and the sensing difference value. The temperature sensing device obtains an error from the first sensing result value and the second sensing result value according to a first reference value and a second reference value. The temperature sensing device calibrates the first compensation value according to the error.

Abstract: A temperature sensing device and a temperature sensing method are provided. The temperature sensing device includes a sensor and a conversion circuit. The sensor generates a first sensing signal and a second sensing signal corresponding to a temperature based on different conditions. The conversion circuit performs a subtraction operation on the first sensing signal and the second sensing signal to obtain a result difference value, calculates a compensation value according to the result difference value and the first sensing signal, multiplies the result difference value and the compensation value to obtain a multiplication value, subtracts the multiplication value from the first sensing signal to generate a first value, adds the multiplication value to the first sensing signal to generate a second value, and divides the first value by the second value to generate an output value. The second value is a constant.

Abstract: A method of measuring chip characteristics includes: outputting an operating voltage to a chip by a test device, wherein the chip comprises a plurality of oscillator circuits configured to generate a plurality of oscillating signals according to the operating voltage; and testing the chip by the test device under a situation that the test device outputs a system clock signal having a first clock period to the chip, including: changing the operating voltage sequentially with the test device until the chip changes from a normal state to a failure state, so as to generate a boundary operating voltage; and recording the plurality of oscillating signals generated according to the boundary operating voltage as measurement data by the test device, wherein the measurement data represents chip characteristics of the chip corresponding to the first clock period.

Abstract: A flying probe includes a test module and a processor. The test module measures a plurality of delta capacitances associated with a plurality of vias in a printed circuit board. The plurality of vias include first, second, third and fourth vias. Each different delta capacitance is measured between a different pair of the vias. The processor compares all the delta capacitances to a threshold value. In response to multiple delta capacitances associated with the first via being greater than or equal to the threshold value, the processor detects a possible via stripping issue for the first via.

Abstract: A comparator circuitry includes an input pair circuit, a load circuit, and a compensation circuit. The input pair circuit is configured to compare a first input signal with a second input signal, in order to control a first bias current. The load circuit is coupled to the input pair circuit, and is configured to output an output signal having a first level from a first output terminal of the load circuit in response to the first bias current. The compensation circuit is coupled to the input pair circuit and the load circuit, and is configured to drain a compensation current from the first output terminal to a voltage source during a period that the load circuit generates the output signal having a first level, in which the voltage source is configured to provide a voltage having a second level.

Abstract: A performance calculation method suitable for a chip is provided. The chip includes oscillator circuit systems configured to generate oscillation signals and to sense operation states of the chip to adjust periods of the oscillation signals. The method includes following operations: when the chip is in a first operation state, constructing a first function according to the periods of the oscillation signals and a first performance value of the chip; when the chip is in a second operation state, constructing a second function according to the periods of the oscillation signals and a second performance value of the chip; adjusting coefficients of the first or second function according to trajectories of graphs of the first and second functions, so that the graphs of the first and second functions intersect at a coordinate point; constructing a performance function of the chip according to the first and second functions.

Abstract: A chip includes at least one oscillator circuitry and a controller circuitry. The at least one oscillator circuitry is disposed at different locations of the chip, and respectively generates a plurality of oscillating signals. The controller circuitry transmits the oscillating signals to an external system, in order to determine a performance of the chip based on the oscillating signals. Each of the at least one oscillator circuitry includes a first oscillator circuit and a second oscillator circuit. The first oscillator circuit senses a variation of a semiconductor device in the chip, in order to generate a first oscillating signal of the oscillating signals. The second oscillator circuit senses a variation of a parasitic component in the chip, in order to generate a second oscillating signal of the oscillating signals.

Abstract: A comparator circuitry includes an input pair circuit, a load circuit, and a compensation circuit. The input pair circuit is configured to compare a first input signal with a second input signal, in order to control a first bias current. The load circuit is coupled to the input pair circuit, and is configured to output an output signal having a first level from a first output terminal of the load circuit in response to the first bias current. The compensation circuit is coupled to the input pair circuit and the load circuit, and is configured to drain a compensation current from the first output terminal to a voltage source during a period that the load circuit generates the output signal having a first level, in which the voltage source is configured to provide a voltage having a second level.

Abstract: A comparator circuitry includes an input pair circuit, a load circuit, and a compensation circuit. The input pair circuit is configured to compare a first input signal with a second input signal, in order to control a first bias current. The load circuit is coupled to the input pair circuit, and is configured to output an output signal having a first level from a first output terminal of the load circuit in response to the first bias current. The compensation circuit is coupled to the input pair circuit and the load circuit, and is configured to drain a compensation current from the first output terminal to a voltage source during the load circuit generates the output signal having a first level, in which the voltage source is configured to provide a voltage having a second level.

Abstract: A chip includes at least one oscillator circuitry and a controller circuitry. The at least one oscillator circuitry is disposed at different locations of the chip, and respectively generates a plurality of oscillating signals. The controller circuitry transmits the oscillating signals to an external system, in order to determine a performance of the chip based on the oscillating signals. Each of the at least one oscillator circuitry includes a first oscillator circuit and a second oscillator circuit. The first oscillator circuit senses a variation of a semiconductor device in the chip, in order to generate a first oscillating signal of the oscillating signals. The second oscillator circuit senses a variation of a parasitic component in the chip, in order to generate a second oscillating signal of the oscillating signals.

Abstract: A comparator circuitry includes an input pair circuit, a load circuit, and a compensation circuit. The input pair circuit is configured to compare a first input signal with a second input signal, in order to control a first bias current. The load circuit is coupled to the input pair circuit, and is configured to output an output signal having a first level from a first output terminal of the load circuit in response to the first bias current. The compensation circuit is coupled to the input pair circuit and the load circuit, and is configured to drain a compensation current from the first output terminal to a voltage source during the load circuit generates the output signal having a first level, in which the voltage source is configured to provide a voltage having a second level.

Abstract: The disclosure provides a cell culture system and a serum-free method for cultivating cells. The cell culture system includes a substratum, wherein the substratum has a surface. A polymer is disposed on the surface of the substratum, wherein the polymer is prepared by polymerizing a first monomer with a second monomer. The first monomer has a structure as represented by Formula (I), and the second monomer has a structure as represented by Formula (II): wherein, R1 is hydrogen or methyl; R2 is methyl, ethyl, or —CH2CH2OCH3; R3 is hydrogen or methyl; and, R4 is hydrogen, —CH2CH2OCOCHCHCOOH, —CH2CH2OCOCH2CH2COOH, or —CH2CH2COOH.

Abstract: The disclosure provides a cell culture system and a serum-free method for cultivating cells. The cell culture system includes a substratum, wherein the substratum has a surface. A polymer is disposed on the surface of the substratum, wherein the polymer is prepared by polymerizing a first monomer with a second monomer. The first monomer has a structure as represented by Formula (I), and the second monomer has a structure as represented by Formula (II): wherein, R1 is hydrogen or methyl; R2 is methyl, ethyl, or —CH2CH2OCH3; R3 is hydrogen or methyl; and, R4 is hydrogen, —CH2CH2OCOCHCHCOOH, —CH2CH2OCOCH2CH2COOH, or —CH2CH2COOH.

Abstract: Provided herein are methods for producing multicellular spheroids or embryoid bodies suitable for providing cells in large scale for various medical applications. In one embodiment, a method of forming embryoid bodies is provided, which comprises culturing undifferentiated HES cells in a culture vessel pre-coated with cellulose and/or its derivatives. In another embodiment, a method of forming hepatic spheroids is provided, which comprises culturing hepatocytes in a culture vessel pre-coated with cellulose and/or its derivatives.

Abstract: Provided herein are methods of proliferating human mesenchymal stem cells obtained from human cord blood and/or human bone marrow aspirates comprising culturing the human mesenchymal stem cells in an environment containing extracellular matrix isolated form human fibroblasts.