Abstract: A charge pump, applied to an OLED display panel and coupled to an output capacitor, includes a first switch to a tenth switch and a first capacitor to a third capacitor. The first switch and second switch are coupled in series between a first voltage and a second voltage lower than first voltage. The third switch is coupled to second voltage. The sixth switch is coupled to first voltage. The seventh switch is coupled to second voltage. The fourth switch, eighth switch and tenth switch are coupled to output capacitor. The first capacitor is coupled between first switch and second switch. The second capacitor is coupled between fifth switch and sixth switch. The third capacitor is coupled between seventh switch and eighth switch. The charge pump is operated in a first phase, a second-A phase, the first phase and a second-B phase in order to provide negative output voltage.

Abstract: A charge pump, applied to an OLED display panel and coupled to an output capacitor, includes a first switch to a tenth switch and a first capacitor to a third capacitor. The first switch and second switch are coupled in series between a first voltage and a second voltage lower than first voltage. The third switch is coupled to second voltage. The sixth switch is coupled to first voltage. The seventh switch is coupled to second voltage. The fourth switch, eighth switch and tenth switch are coupled to output capacitor. The first capacitor is coupled between first switch and second switch. The second capacitor is coupled between fifth switch and sixth switch. The third capacitor is coupled between seventh switch and eighth switch. The charge pump is operated in a first phase, a second-A phase, the first phase and a second-B phase in order to provide negative output voltage.

Abstract: A charge pump circuit includes a first switch˜a fourth switch, a capacitor, a current source, a first resistor, a second resistor, an amplifier, another current source, a current mirror, a skip detection circuit, a switch generation circuit and a control unit. A method includes: (a) starting the charge pump circuit; (b) operating the charge pump circuit in a first phase, wherein the first switch and second switch are conducted and the third switch and fourth switch are disconnected; (c) operating the charge pump circuit in a second phase, wherein the third switch and fourth switch are conducted and the first switch and second switch are disconnected; (d) determining whether a detected voltage in the skip detection circuit is higher than a threshold voltage; and (e) selectively performing step (b) or (c) again according to determination result of step (d).

Abstract: A charge pump circuit includes a first switch˜a fourth switch, a capacitor, a current source, a first resistor, a second resistor, an amplifier, another current source, a current mirror, a skip detection circuit, a switch generation circuit and a control unit. A method includes: (a) starting the charge pump circuit; (b) operating the charge pump circuit in a first phase, wherein the first switch and second switch are conducted and the third switch and fourth switch are disconnected; (c) operating the charge pump circuit in a second phase, wherein the third switch and fourth switch are conducted and the first switch and second switch are disconnected; (d) determining whether a detected voltage in the skip detection circuit is higher than a threshold voltage; and (e) selectively performing step (b) or (c) again according to determination result of step (d).

Abstract: A bootstrap circuit includes: a charging voltage source; a charging diode, having an anode coupled to the charging voltage source; a high-voltage transistor, having a control terminal defined as a first connecting node and a channel coupled between a cathode of the charging diode and a bootstrap capacitor; a logic control circuit, having a first and a second logic outputs, and a logic input for receiving a charging command; a high-voltage control transistor, having a control terminal defined as a second connecting node and a channel coupled between charging voltage source and the first connecting node; a cut-off resistor, coupled between the first and the second connecting nodes; a charging control transistor, having a channel coupled between the second connecting node and a ground terminal, and a control terminal coupled to the second logic output; a control capacitor, coupled between the first connecting node and the first logic output.

Abstract: A floating gate driver uses a single-end level shifter to translate a set signal and a reset signal induced by a rising edge and a falling edge of a switch signal to a common output terminal to generate an output voltage for a bistable circuit to generate a level shifted switch signal. Under control of a well transient detect signal asserted by detecting noise in the output voltage, a masking circuit between the single-end level shifter and the bistable circuit masks noise in the output voltage. This configuration has lower area penalty and better noise immunity.

Abstract: A floating gate driver uses a single-end level shifter to translate a set signal and a reset signal induced by a rising edge and a falling edge of a switch signal to a common output terminal to generate an output voltage for a bistable circuit to generate a level shifted switch signal. Under control of a well transient detect signal asserted by detecting noise in the output voltage, a masking circuit between the single-end level shifter and the bistable circuit masks noise in the output voltage. This configuration has lower area penalty and better noise immunity.

Abstract: A high voltage half-bridge driver circuit has a high voltage terminal and a floating node to be connected with a high side switch therebetween. When turning on the high side switch, a high voltage offset detection circuit detects a voltage related to the voltage at the floating node for triggering a zero voltage switching signal.

Abstract: A floating gate driver uses a single-end level shifter to translate a set signal and a reset signal induced by a rising edge and a falling edge of a switch signal to a common output terminal to generate an output voltage for a bistable circuit to generate a level shifted switch signal. Under control of a well transient detect signal asserted by detecting noise in the output voltage, a masking circuit between the single-end level shifter and the bistable circuit masks noise in the output voltage. This configuration has lower area penalty and better noise immunity.

Abstract: A bootstrap circuit includes: a charging voltage source; a charging diode, having an anode coupled to the charging voltage source; a high-voltage transistor, having a control terminal defined as a first connecting node and a channel coupled between a cathode of the charging diode and a bootstrap capacitor; a logic control circuit, having a first and a second logic outputs, and a logic input for receiving a charging command; a high-voltage control transistor, having a control terminal defined as a second connecting node and a channel coupled between charging voltage source and the first connecting node; a cut-off resistor, coupled between the first and the second connecting nodes; a charging control transistor, having a channel coupled between the second connecting node and a ground terminal, and a control terminal coupled to the second logic output; a control capacitor, coupled between the first connecting node and the first logic output.

Abstract: A high voltage H-bridge driver circuit has a high voltage terminal and a floating node to be connected with a high side switch therebetween. When turning on the high side switch, a high voltage offset detection circuit detects a voltage related to the voltage at the floating node for triggering a zero voltage switching signal.

Abstract: A floating gate driver circuit includes a level shifter, a pass element, a bistable circuit and a control logic circuit, to shift the voltage level of a control signal from a lower one to a higher one. The level shifter or the pass element has loads dynamically controlled by the control logic circuit to filter malfunction caused by dv/dt noise induced by a floating node.

Abstract: A high voltage half-bridge driver circuit has a high voltage terminal and a floating node to be connected with a high side switch therebetween. When turning on the high side switch, a high voltage offset detection circuit detects a voltage related to the voltage at the floating node for triggering a zero voltage switching signal.

Abstract: The present invention provides a high voltage device including a shielding metal layer to reduce the noise interference from a high voltage source. The high voltage device includes a substrate, a field oxide layer, a gate layer, a shielding metal layer, and a high voltage interconnection line. The substrate includes a first doped region and a second doped region separated from each other. The field oxide layer is disposed on the substrate. The gate layer is disposed above the field oxide layer. The high voltage interconnection line is coupled to the first doped region and passes above but not below the first shielding metal layer.

Abstract: A floating gate driver includes a level shifter to transmit a set signal and a reset signal to a first output terminal and a second output terminal, respectively. The level shifter includes a first high-voltage transistor, a first current limiter and a first input transistor connected in series between the first output terminal and a ground terminal, and a second high-voltage transistor, a second current limiter and a second input transistor connected in series between the second output terminal and the ground terminal, and the first and second high-voltage transistors are remained on. With this arrangement, the level shifter can transmit signals from low side to high side under better safe operating area and has better noise immunity.

Abstract: The present invention discloses a control circuit of a switching regulator wherein a confirmation signal is generated to confirm that an upper gate switch has been turned off, to avoid shoot-through. The confirmation signal is generated by obtaining an upper gate sampling signal from a transistor in a level shift circuit which receives a resetting signal for turning off the upper gate switch.

Abstract: A floating gate driver circuit includes a level shifter, a pass element, a bistable circuit and a control logic circuit, to shift the voltage level of a control signal from a lower one to a higher one. The level shifter or the pass element has loads dynamically controlled by the control logic circuit to filter malfunction caused by dv/dt noise induced by a floating node.

Abstract: The present invention discloses a control circuit of a switching regulator wherein a confirmation signal is generated to confirm that an upper gate switch has been turned off, to avoid shoot-through. The confirmation signal is generated by obtaining an upper gate sampling signal from a transistor in a level shift circuit which receives a resetting signal for turning off the upper gate switch.