Abstract: A memory device includes a memory array, a first latch and a first logic element. The memory array is configured to operate according to a first global write signal. The first latch is configured to generate a first latch write data based on a clock signal. The first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.

Abstract: A memory device includes a local input/output circuit and a main input/output circuit. The local input/output circuit is configured to generate a first local write signal based on a first global write signal and a second global write signal, and configured to transmit the first local write signal to a plurality of first bit lines. The main input/output circuit include a first latch and logic elements. The first latch is configured to generate a first bit write mask signal based on a clock signal. The logic elements are configured to generate the first global write signal and the second global write signal based on the clock signal and the first bit write mask signal.

Abstract: A memory device includes a local input/output circuit and a main input/output circuit. The local input/output circuit is configured to generate a first local write signal based on a first global write signal and a second global write signal, and configured to transmit the first local write signal to a plurality of first bit lines. The main input/output circuit include a first latch and logic elements. The first latch is configured to generate a first bit write mask signal based on a clock signal. The logic elements are configured to generate the first global write signal and the second global write signal based on the clock signal and the first bit write mask signal.

Abstract: A circuit includes a first inverter, a second inverter, a first header circuit and a second header circuit. The first inverter is configured to convert a first global write signal into a first local write signal transmitted to a complement bit line. The second inverter is configured to convert a second global write signal into a second local write signal transmitted to a bit line. The first header circuit connects or disconnects a power terminal of the first inverter with a positive reference voltage supply in response to a write enable signal and the second global write signal. The second header circuit connects or disconnects a power terminal of the second inverter with the positive reference voltage supply in response to a write enable signal and the first global write signal.

Abstract: A circuit includes a first inverter, a second inverter, a first header circuit and a second header circuit. The first inverter is configured to convert a first global write signal into a first local write signal transmitted to a complement bit line. The second inverter is configured to convert a second global write signal into a second local write signal transmitted to a bit line. The first header circuit connects or disconnects a power terminal of the first inverter with a positive reference voltage supply in response to a write enable signal and the second global write signal. The second header circuit connects or disconnects a power terminal of the second inverter with the positive reference voltage supply in response to a write enable signal and the first global write signal.