Patents by Inventor Pei Lin

Pei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11554789
    Abstract: A method for providing assistance in driving includes capturing an image of a second moving vehicle when a first moving vehicle is moving and obtaining basic information of the second moving vehicle according to the image thereof, the basic information of the second moving vehicle comprising weight information of the second moving vehicle. Driving information of the first moving vehicle is obtained, and a safe distance between the first moving vehicle and the second moving vehicle is determined according to the driving information of the first moving vehicle and the basic information of the second moving vehicle. The current distance between the first moving vehicle and the second moving vehicle is detected, and a warning is output if the distance between the first moving vehicle and the second moving vehicle is less than the safe distance.
    Type: Grant
    Filed: October 11, 2020
    Date of Patent: January 17, 2023
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Chih-Pu Hsu, Jian-Cheng Lin, Pei-Lin Chen, Tsung-Chun Tseng, Chien-Chun Chang
  • Patent number: 11551626
    Abstract: An electronic paper display device and an operation method thereof are provided. The electronic paper display device includes an electronic paper display panel and a timing controller. The timing controller includes a first image buffer memory, a second image buffer memory, and an update buffer memory. The timing controller receives a touch track data. The first image buffer memory and the second image buffer memory are a ping-pong buffer architecture, and receive a video stream in staggered timing. The second image buffer memory receives the touch track data and simultaneously updates a current display screen data stored in the update buffer memory when the first image buffer memory receives the video stream to update the current display screen data into the update buffer memory. The timing controller drives the electronic paper display panel according to the current display screen data.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: January 10, 2023
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Lung Cheng, Shu-Cheng Liu, Pei-Lin Tien, Cheng-Hsin Chu, Chi-Mao Hung
  • Publication number: 20220398410
    Abstract: A manufacturing data analyzing method and a manufacturing data analyzing device are provided. The manufacturing data analyzing method includes the following steps. Each of at least one numerical data, at least one image data and at least one text data is transformed into a vector. The vectors are gathered to obtain a combined vector. The combined vector is inputted into an inference model to obtain a defect cause and a modify suggestion.
    Type: Application
    Filed: June 10, 2021
    Publication date: December 15, 2022
    Inventors: Ching-Pei LIN, Ming-Tsung YEH, Chuan-Guei WANG, Ji-Fu KUNG
  • Patent number: 11508324
    Abstract: An E-paper display device including an E-paper display panel and a display driver is provided. The E-paper display panel displays an image. The image includes a first frame and a second frame. The display driver is coupled to the E-paper display panel. The display driver drives the E-paper display panel to display the image. The display driver drives a first pixel group of the E-paper display panel in a first polarity and drives a second pixel group of the E-paper display panel in a second polarity to display the first frame during a first frame period. The first pixel group and the second pixel group are arranged in interlacing. The display driver drives the second pixel group of the E-paper display panel in the first polarity to display the second frame during a second frame period. Moreover, a method for driving an E-paper display panel is also provided.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: November 22, 2022
    Assignee: E Ink Holdings Inc.
    Inventors: Shu-Cheng Liu, Hsiao-Lung Cheng, Pei-Lin Tien, Chi-Mao Hung
  • Publication number: 20220364715
    Abstract: A lighting assembly includes a hollow post module, a lighting module, and a control module. The control module includes a casing, a circuit board, a processor, and a capacitive proximity sensor module. The casing has a casing body and a casing cover to define a receiving space. The casing cover has an outer contact surface exposed from the post module and an inner contact surface. The circuit board is elongated along a lengthwise direction of the hollow post module in the receiving space and perpendicular to the inner contact surface. The processor is connected to the lighting module. The capacitive proximity sensor module connects the circuit board and processor and abut the inner contact surface.
    Type: Application
    Filed: November 2, 2021
    Publication date: November 17, 2022
    Inventor: Pei-Lin HSIEH
  • Patent number: 11501725
    Abstract: An e-paper display device, including a driver circuit. The driver circuit is coupled to the e-paper display panel and drives the e-paper display panel to display one or more line segments, which include a current display line segment and a target display line segment. During a frame period, the driver circuit pre-drives a display area to display a first color according to the current display line segment. At least part of the target display line segment is located in the display area. During a next frame period, the driver circuit drives a part of the display area excluding the target display line segment to display a second color and a part of the display area including the target display line segment to display the first color according to the target display line segment. A method for driving an e-paper display panel.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: November 15, 2022
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Lung Cheng, Shu-Cheng Liu, Pei-Lin Tien, Chi-Mao Hung
  • Publication number: 20220301509
    Abstract: An electronic paper display device and an operation method thereof are provided. The electronic paper display device includes an electronic paper display panel and a timing controller. The timing controller includes a first image buffer memory, a second image buffer memory, and an update buffer memory. The timing controller receives a touch track data. The first image buffer memory and the second image buffer memory are a ping-pong buffer architecture, and receive a video stream in staggered timing. The second image buffer memory receives the touch track data and simultaneously updates a current display screen data stored in the update buffer memory when the first image buffer memory receives the video stream to update the current display screen data into the update buffer memory. The timing controller drives the electronic paper display panel according to the current display screen data.
    Type: Application
    Filed: January 24, 2022
    Publication date: September 22, 2022
    Applicant: E Ink Holdings Inc.
    Inventors: Hsiao-Lung Cheng, Shu-Cheng Liu, Pei-Lin Tien, Cheng-Hsin Chu, Chi-Mao Hung
  • Publication number: 20220291801
    Abstract: A driving circuit of a display and an operation method of a timing controller are provided. The driving circuit of the display includes a timing controller. The timing controller is coupled to a general purpose input/output (GPIO) pin of the touch driver. The timing controller receives an instruction signal via the general purpose input/output pin of the touch driver. The timing controller starts a detection period according to a main falling edge of the instruction signal. The timing controller determines a current operating status of the touch driver according to a number of sub-falling edges of the instruction signal during the detection period.
    Type: Application
    Filed: January 21, 2022
    Publication date: September 15, 2022
    Applicant: E Ink Holdings Inc.
    Inventors: Hsiao-Lung Cheng, Shu-Cheng Liu, Pei-Lin Tien, I-Shin Lo, Chi-Mao Hung
  • Patent number: 11443825
    Abstract: Provided is a failure mode analysis method for a memory device including the following steps. A wafer is scanned by a test system to generate a failure pattern of the wafer, and a failure count of a single-bit in the wafer is obtained by a test program. A single-bit grouping table is defined according to a word-line layout, a bit-line layout, and an active area layout. A core group and a gap group are formed through grouping in at least one process in a self-aligned double patterning process. Failure counts of single-bits in the core group and the gap group are respectively counted to generate core failure data and gap failure data.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: September 13, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Yu-Feng Ho, Kuo-Min Liao, Yu-Pei Lin
  • Publication number: 20220285224
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a spacer over a side of the gate stack. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a first recess, the dielectric layer has an upper portion and a first lower portion, the upper portion is over the first recess, the first recess is between the first lower portion and the spacer, and the upper portion has a convex curved sidewall.
    Type: Application
    Filed: May 24, 2022
    Publication date: September 8, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Heng TSAI, Chun-Sheng LIANG, Pei-Lin WU, Yi-Ren CHEN, Shih-Hsun CHANG
  • Patent number: 11403728
    Abstract: An automatic adjusting method for equipment and a smart adjusting device using the same are provided. The automatic adjusting method of the equipment includes the following steps. A template frame from the equipment is obtained in an initial period. Several clear frames are obtained in one window period. Each of the template frame and the clear frame has a pixel variation. The pixel variation of the template frame is the largest in the initial period. The pixel variation of each of the clear frame is greater than a threshold. Each of the clear frame is compared with the template frame to obtain an offset. A statistical value of the offsets is calculated. A parameter of the equipment is adjusted to reduce the statistical value.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: August 2, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Chi Lin, Li-Hsin Yang, Ching-Pei Lin, Ming-Wei Chen, Wei-Hong Zhu
  • Publication number: 20220220015
    Abstract: A multi-valve water treatment system (100) comprising a motor (3) having an output shaft, a driven shaft (2) fixed to the output shaft such that the driven shaft (2) is driven by the motor (3) when the motor (3) is activated, the driven shaft (2) having at least one cam (21A-21C) disposed at an axial position along the driven shaft (2), and a valve assembly (6) including, a valve actuator (61A-61C) urged into engagement with the driven shaft (2) at the axial position, such that the valve actuator (61A-61C) is moved axially upon engagement with the cam (21A-21C), a fluid flow housing (1) having a fluid outlet (411) and at least one fluid inlet (412A-412C) selectively sealingly engaged by the valve actuator (61A-61C) such that the fluid inlet (412A-412C) selectively allows flow from the fluid inlet (412A-412C) to the fluid outlet (411) depending on the position of the valve actuator (61A-61C), and a diaphragm (5) sealingly isolating the fluid inlet (412A-412C) and the fluid outlet (411) of the housing (1) from
    Type: Application
    Filed: April 15, 2020
    Publication date: July 14, 2022
    Inventors: Zhi Xiong HUANG, Yong Gui CHEN, Pei Lin CHEN
  • Publication number: 20220222162
    Abstract: An operation method and an operation device of a failure detection and classification (FDC) model are provided. The operation method of the FDC model includes the following steps. A plurality of raw traces are continuously obtained. If the raw traces have started to be changed from the first waveform to the second waveform, whether at least N pieces in the race traces have been changed to the second waveform is determined. If at least N pieces in the raw traces have been changed to the second waveform, the raw traces which have been changed to the second waveform are automatically segmented to obtain several windows. An algorithm is automatically set for each of the windows. Through each of the algorithms, an indicator of each of the windows is obtained. The FDC model is retrained based on these indicators.
    Type: Application
    Filed: February 22, 2021
    Publication date: July 14, 2022
    Inventors: Ching-Pei LIN, Ji-Fu KUNG, Te-Hsuan CHEN, Yi-Lin HUNG
  • Publication number: 20220220013
    Abstract: A water treatment system protects chlorine generator electrodes from miming dry. The system includes a water detection electrode (222) disposed above the chlorine generator electrode (223), and an outlet (12) at a height similar to the water detection electrode (222). If enough water is displaced from the housing (1) of the water treatment system by bubbles (4) generated by the energized chlorine generator, the water detection electrode (222) will cease to be bathed in water and will emit a signal indicative of this “dry” condition. The signal can be used to interrupt electrical power to the chlorine generator, thereby ensuring that the chlorine generator will not displace the water bathing it and therefore will not run dry.
    Type: Application
    Filed: April 15, 2020
    Publication date: July 14, 2022
    Inventors: Zhi Xiong HUANG, Yong Gui CHEN, Pei Lin CHEN
  • Publication number: 20220223113
    Abstract: An electronic paper display and a driving method thereof are provided. The electronic paper display includes an electronic paper display panel, a touch panel and a processing circuit. The touch panel outputs a first touch coordinate of a current touch and a second touch coordinate of a next touch. The processing circuit executes a filter module and a line drawing module. The filter module outputs a first measured position data and a first predicted position data to the line drawing module. The line drawing module drives the electronic paper display panel to display a first predicted track. The filter module outputs a second measured position data to the line drawing module. The line drawing module determines whether a second track display coordinate corresponding to the second measured position data is equal to the first predicted display coordinate to correct the first predicted track.
    Type: Application
    Filed: March 30, 2022
    Publication date: July 14, 2022
    Applicant: E Ink Holdings Inc.
    Inventors: Shu-Cheng Liu, Hsiao-Lung Cheng, Pei-Lin Tien, Chi-Mao Hung, Wen-Pin Liu
  • Patent number: 11367727
    Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: June 21, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
  • Patent number: 11367378
    Abstract: A driving method includes the following steps: driving a first dummy pixel circuit according to a first test signal, and driving a display pixel circuit according to a driving signal, wherein the first test signal is maintained at a value corresponding to a first gray level; detecting a detection voltage change value cross a light-emitting element in the display pixel circuit is driven for a driving time, and detecting a first test voltage change value cross a light-emitting element in the first dummy pixel circuit is driven for the driving time; and adjusting the driving signal according to the detection voltage change value, the first test voltage change value and a second test voltage change value, wherein the second test voltage change value is obtained by detecting a second dummy pixel circuit or from a memory unit.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: June 21, 2022
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Pei-Lin Hsieh, Che-Ming Hsu
  • Patent number: 11367728
    Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: June 21, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
  • Publication number: 20220172796
    Abstract: Provided is a failure mode analysis method for a memory device including the following steps. A wafer is scanned by a test system to generate a failure pattern of the wafer, and a failure count of a single-bit in the wafer is obtained by a test program. A single-bit grouping table is defined according to a word-line layout, a bit-line layout, and an active area layout. A core group and a gap group are formed through grouping in at least one process in a self-aligned double patterning process. Failure counts of single-bits in the core group and the gap group are respectively counted to generate core failure data and gap failure data.
    Type: Application
    Filed: December 2, 2020
    Publication date: June 2, 2022
    Applicant: Winbond Electronics Corp.
    Inventors: Yu-Feng Ho, Kuo-Min Liao, Yu-Pei Lin
  • Patent number: 11348841
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate, wherein the gate stack has a first portion and a second portion under the first portion, and the first portion is wider than the second portion. The semiconductor device structure includes a first spacer and a second spacer over opposite sides of the gate stack. The first spacer has a first upper portion and a first lower portion, the second spacer has a second upper portion and a second lower portion. The first spacer has a first recess, the first upper portion is between the first recess and the gate stack, the first lower portion is under the first recess, and the first recess has a first inner wall facing away from the gate stack.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Heng Tsai, Chun-Sheng Liang, Pei-Lin Wu, Yi-Ren Chen, Shih-Hsun Chang