Patents by Inventor Pei-Ling GAO

Pei-Ling GAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240387533
    Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a first fin extending along a first direction, a second fin extending parallel to the first fin, and a gate structure over and wrapping around the first fin and the second fin, the gate structure extending along a second direction perpendicular to the first direction. The first fin bents away from the second fin along the second direction and the second fin bents away from the first fin along the second direction.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Jiun-Ming Kuo, Pei-Ling Gao, Chen-Hsuan Liao, Hung-Ju Chou, Chih-Chung Chang, Che-Yuan Hsu
  • Patent number: 12136651
    Abstract: A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Shan Lu, Hung-Ju Chou, Pei-Ling Gao, Chen-Hsuan Liao, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu
  • Patent number: 11923250
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Ju Chou, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Gao, Chen-Hsuan Liao
  • Publication number: 20240021612
    Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a first fin extending along a first direction, a second fin extending parallel to the first fin, and a gate structure over and wrapping around the first fin and the second fin, the gate structure extending along a second direction perpendicular to the first direction. The first fin bents away from the second fin along the second direction and the second fin bents away from the first fin along the second direction.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 18, 2024
    Inventors: Jiun-Ming Kuo, Pei-Ling Gao, Chen-Hsuan Liao, Hung-Ju Chou, Chih-Chung Chang, Che-Yuan Hsu
  • Publication number: 20230387213
    Abstract: A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Yu-Shan Lu, Hung-Ju Chou, Pei-Ling Gao, Chen-Hsuan Liao, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu
  • Patent number: 11791336
    Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a first fin extending along a first direction, a second fin extending parallel to the first fin, and a gate structure over and wrapping around the first fin and the second fin, the gate structure extending along a second direction perpendicular to the first direction. The first fin bents away from the second fin along the second direction and the second fin bents away from the first fin along the second direction.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun-Ming Kuo, Pei-Ling Gao, Chen-Hsuan Liao, Hung-Ju Chou, Chih-Chung Chang, Che-Yuan Hsu
  • Patent number: 11705372
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Ju Chou, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Gao, Chen-Hsuan Liao
  • Publication number: 20230008005
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Application
    Filed: July 28, 2022
    Publication date: January 12, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Ju Chou, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Gao, Chen-Hsuan Liao
  • Publication number: 20210257360
    Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a first fin extending along a first direction, a second fin extending parallel to the first fin, and a gate structure over and wrapping around the first fin and the second fin, the gate structure extending along a second direction perpendicular to the first direction. The first fin bents away from the second fin along the second direction and the second fin bents away from the first fin along the second direction.
    Type: Application
    Filed: September 15, 2020
    Publication date: August 19, 2021
    Inventors: Jiun-Ming Kuo, Pei-Ling Gao, Chen-Hsuan Liao, Hung-Ju Chou, Chih-Chung Chang, Che-Yuan Hsu
  • Publication number: 20210257462
    Abstract: A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance.
    Type: Application
    Filed: December 18, 2020
    Publication date: August 19, 2021
    Inventors: Yu-Shan Lu, Hung-Ju Chou, Pei-Ling Gao, Chen-Hsuan Liao, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu
  • Publication number: 20210249312
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Application
    Filed: February 11, 2020
    Publication date: August 12, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Ju CHOU, Chih-Chung CHANG, Jiun-Ming KUO, Che-Yuan HSU, Pei-Ling GAO, Chen-Hsuan LIAO