Patents by Inventor Pei-Ling Hsieh

Pei-Ling Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240356199
    Abstract: A method of manufacturing an electronic device includes: providing a composite structure, wherein the composite structure comprises a core dielectric layer with two conductive layers formed on two opposite surfaces of the core dielectric layer; thinning the two conductive layers to form two thinned conductive layers; forming an antenna pattern using one of the two thinned conductive layers; forming an antenna package to encapsulate the antenna pattern therein; forming a circuit pattern by patterning the other one of the two thinned conductive layers; and forming a chip package to encapsulate the circuit pattern therein, wherein the chip package is electrically coupled to the antenna package.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Hsuan Lee, Ching-Hua Hsieh, Chien-Ling Hwang, Yu-Ting Chiu, Jui-Chang Kuo
  • Publication number: 20240312859
    Abstract: A manufacturing method of a package system includes: providing a base plate with a first thermal interface material (TIM) layer; placing a semiconductor package on the first TIM layer over the base plate, wherein the semiconductor package comprises a plurality of packaging units arranged in an array and a plurality of electrical connectors surrounding the array of the plurality of packaging units; stacking a gasket and a top plate on the array of the plurality of packaging units, wherein the gasket is interposed between the top plate and the array of the plurality of packaging units; and securing the top plate, the gasket, the plurality of packaging units, and the base plate together through a plurality of fasteners, wherein each of the plurality of fasteners is arranged at a gap between two of the adjacent packaging units.
    Type: Application
    Filed: May 26, 2024
    Publication date: September 19, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Hsuan Lee, Ching-Hua Hsieh, Chien-Ling Hwang
  • Publication number: 20240307471
    Abstract: A method against coronavirus infection includes administering to a subject in need thereof a pharmaceutical composition containing a water-extracted product of Melastoma malabathricum root.
    Type: Application
    Filed: September 11, 2023
    Publication date: September 19, 2024
    Inventors: Pei-Wen Hsieh, Tsong-Long Hwang, Yu-Ling Huang
  • Patent number: 12062832
    Abstract: A method of manufacturing an electronic device includes providing a core dielectric layer with two conductive layers formed on two opposite surfaces of the core dielectric layer, and removing at least a portion of each of the two conductive layers to respectively form an antenna pattern and a circuit pattern of a chip package at the two opposite surfaces of the core dielectric layer.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: August 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Hsuan Lee, Ching-Hua Hsieh, Chien-Ling Hwang, Yu-Ting Chiu, Jui-Chang Kuo
  • Patent number: 12040247
    Abstract: A package system and a manufacturing method thereof are provided. The package system includes a semiconductor package and a thermal-dissipating structure. The semiconductor package includes a first surface and a second surface opposing to each other, and a planarity of the second surface is greater than that of the first surface. The thermal-dissipating structure includes a first plate secured to the semiconductor package, a gasket interposed between the first plate and the semiconductor package, a second plate secured to the semiconductor package opposite to the first plate, and a first thermal interface material layer interposed between the second plate and the second surface of the semiconductor package. The gasket includes a plurality of hollow regions corresponding to portions of the first surface of the semiconductor package.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Hsuan Lee, Ching-Hua Hsieh, Chien-Ling Hwang
  • Patent number: D515571
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: February 21, 2006
    Assignee: Hannspree, Inc.
    Inventor: Pei-Ling Hsieh
  • Patent number: D515572
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: February 21, 2006
    Assignee: Hannspree, Inc.
    Inventor: Pei-Ling Hsieh
  • Patent number: D516067
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: February 28, 2006
    Assignee: Hannspree, Inc.
    Inventor: Pei-Ling Hsieh