Patents by Inventor Pei-Lun JHENG

Pei-Lun JHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250031365
    Abstract: A memory structure including a substrate, charge storage layers, and a gate is provided. The charge storage layers are located on the substrate. The gate is located on the substrate on one side of the charge storage layers. The gate extends along a first direction. The gate has a protruding portion protruding along a second direction. The second direction intersects the first direction. The protruding portion is located between two adjacent charge storage layers arranged along the first direction.
    Type: Application
    Filed: August 4, 2023
    Publication date: January 23, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Hsin-Chieh Lin, Po-Jui Chiang, Pei Lun Jheng, Chao-Sheng Cheng, Ming-Jen Chang, Ko Chin Chang, Yu Ming Liu
  • Patent number: 11658227
    Abstract: A method for manufacturing a semiconductor structure is provided. The method comprises the following steps. A first silicon-containing gate electrode is formed on a semiconductor substrate in a first region. A second silicon-containing gate electrode is formed on the semiconductor substrate in a second region. A gate silicide element is formed on an upper surface of the first silicon-containing gate electrode. A source silicide element and a drain silicide element are formed on the semiconductor substrate on opposing sides of the second silicon-containing gate electrode respectively. The gate silicide element, the source silicide element and the drain silicide element are formed simultaneously.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: May 23, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pei-Lun Jheng, Chao-Sheng Cheng
  • Publication number: 20220140102
    Abstract: A method for manufacturing a semiconductor structure is provided. The method comprises the following steps. A first silicon-containing gate electrode is formed on a semiconductor substrate in a first region. A second silicon-containing gate electrode is formed on the semiconductor substrate in a second region. A gate silicide element is formed on an upper surface of the first silicon-containing gate electrode. A source silicide element and a drain silicide element are formed on the semiconductor substrate on opposing sides of the second silicon-containing gate electrode respectively. The gate silicide element, the source silicide element and the drain silicide element are formed simultaneously.
    Type: Application
    Filed: January 6, 2022
    Publication date: May 5, 2022
    Inventors: Pei-Lun JHENG, Chao-Sheng CHENG
  • Patent number: 11251283
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a semiconductor substrate, a silicon-containing gate electrode, and at least two gate silicide strips. The silicon-containing gate electrode is on the semiconductor substrate. The at least two gate silicide strips are on an upper surface of the silicon-containing gate electrode.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: February 15, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pei-Lun Jheng, Chao-Sheng Cheng
  • Publication number: 20210305395
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a semiconductor substrate, a silicon-containing gate electrode, and at least two gate silicide strips. The silicon-containing gate electrode is on the semiconductor substrate. The at least two gate silicide strips are on an upper surface of the silicon-containing gate electrode.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 30, 2021
    Inventors: Pei-Lun JHENG, Chao-Sheng CHENG