Patents by Inventor Pei-Ming Daniel Chow

Pei-Ming Daniel Chow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9685432
    Abstract: A multi-gate Schottky depletion-mode field effect transistor (FET), at least one diode and two resistors comprise a compact electrostatic discharge (ESD) protection structure. This ESD protection structure can be laid out in a smaller area than typical multiple diode ESD devices. The multi-gate FET may comprise various types of high-electron-mobility transistor (HEMT) devices, e.g., (pseudomorphic) pHEMT, (metamorphic) mHEMT, induced HEMT. The multiple gates of the Schottky field effect device are used to form an ESD trigger and charge draining paths for protection of circuits following the ESD protection device. Both single and dual polarity ESD protection devices may be provided on an integrated circuit die for protection of input-output circuits thereof.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: June 20, 2017
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Pei-Ming Daniel Chow, Jing Zhu, Yon-Lin Kok, Steven Schell
  • Publication number: 20160372459
    Abstract: A multi-gate Schottky depletion-mode field effect transistor (FET), at least one diode and two resistors comprise a compact electrostatic discharge (ESD) protection structure. This ESD protection structure can be laid out in a smaller area than typical multiple diode ESD devices. The multi-gate FET may comprise various types of high-electron-mobility transistor (HEMT) devices, e.g., (pseudomorphic) pHEMT, (metamorphic) mHEMT, induced HEMT. The multiple gates of the Schottky field effect device are used to form an ESD trigger and charge draining paths for protection of circuits following the ESD protection device. Both single and dual polarity ESD protection devices may be provided on an integrated circuit die for protection of input-output circuits thereof.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 22, 2016
    Applicant: Microchip Technology Incorporated
    Inventors: Pei-Ming Daniel Chow, Jing Zhu, Yon-Lin Kok, Steven Schell
  • Patent number: 9431390
    Abstract: A multi-gate Schottky depletion-mode field effect transistor (FET), at least one diode and two resistors comprise a compact electrostatic discharge (ESD) protection structure. This ESD protection structure can be laid out in a smaller area than typical multiple diode ESD devices. The multi-gate FET may comprise various types of high-electron-mobility transistor (HEMT) devices, e.g., (pseudomorphic) pHEMT, (metamorphic) mHEMT, induced HEMT. The multiple gates of the Schottky field effect device are used to form an ESD trigger and charge draining paths for protection of circuits following the ESD protection device. Both single and dual polarity ESD protection devices may be provided on an integrated circuit die for protection of input-output circuits thereof.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: August 30, 2016
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Pei-Ming Daniel Chow, Yon-Lin Kok, Jing Zhu, Steven Schell
  • Publication number: 20140327048
    Abstract: A multi-gate Schottky depletion-mode field effect transistor (FET), at least one diode and two resistors comprise a compact electrostatic discharge (ESD) protection structure. This ESD protection structure can be laid out in a smaller area than typical multiple diode ESD devices. The multi-gate FET may comprise various types of high-electron-mobility transistor (HEMT) devices, e.g., (pseudomorphic) pHEMT, (metamorphic) mHEMT, induced HEMT. The multiple gates of the Schottky field effect device are used to form an ESD trigger and charge draining paths for protection of circuits following the ESD protection device. Both single and dual polarity ESD protection devices may be provided on an integrated circuit die for protection of input-output circuits thereof.
    Type: Application
    Filed: May 1, 2014
    Publication date: November 6, 2014
    Inventors: Pei-Ming Daniel Chow, Yon-Lin Kok, Jing Zhu, Steven Schell
  • Patent number: 8264272
    Abstract: A front-end module comprises a plurality of chips that includes first and second functional blocks and an interconnection circuit. The first functional block is formed using a first process type and includes a digital control circuit that generates a digital control signal in response to an external control signal from outside the front end module. The second functional block is formed using a second process type and includes a digitally controlled circuit controlled by the digital control signal generated by the first functional block. The second process type is different from the first process type. The interconnection circuit couples the digital control circuit and the digitally controlled circuit to provide the digital control signal to the digitally controlled circuit. In one aspect, the first functional block may be a low noise amplifier formed by a pseudomorphic high electron mobility transistor process.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: September 11, 2012
    Assignee: Microchip Technology Incorporated
    Inventors: Liyang Zhang, Pei-Ming Daniel Chow, Mau-Chung Frank Chang
  • Patent number: 8115552
    Abstract: A step gain amplifier has an amplifier with an input and an output, and a bias circuit connected to the input and to a bias node. A passive feedback circuit using only passive elements connects the output to the input. A control circuit is connected to the bias circuit at the bias node.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: February 14, 2012
    Assignee: Microchip Technology Incorporated
    Inventors: Bun Kobayashi, Steven W. Schell, Yonghan Chris Kim, Pei-Ming Daniel Chow, Mau-Chung Frank Chang
  • Publication number: 20110169573
    Abstract: A step gain amplifier has an amplifier with an input and an output, and a bias circuit connected to the input and to a bias node. A passive feedback circuit using only passive elements connects the output to the input. A control circuit is connected to the bias circuit at the bias node.
    Type: Application
    Filed: January 11, 2010
    Publication date: July 14, 2011
    Inventors: Bun Kobayashi, Steven W. Schell, Yonghan Chris Kim, Pei-Ming Daniel Chow, Mau-Chung Frank Chang
  • Patent number: 7965152
    Abstract: An attenuator system comprises an attenuator and a control circuit for controlling the attenuation of the attenuator. In one embodiment, the attenuator comprises two diodes or two diode connected transistors, and the control circuit comprises two transistors as the only active devices. In another embodiment, the control circuit comprises another transistor in a shut down circuit.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: June 21, 2011
    Assignee: Microchip Technology Incorporated
    Inventors: Bun Kobayashi, Steven W. Schell, Pei-Ming Daniel Chow, Mau-Chung Frank Chang
  • Patent number: 7893684
    Abstract: An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit for generating a power control voltage having a voltage characteristic that offsets temperature characteristics of the received RF signal. The amplifier circuit further comprises a power amplifier coupled to the bias circuit. The power amplifier includes a driver stage providing the RF signal. The detection circuit compensates temperature variation of the inputted detection voltage of the received RF signal.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: February 22, 2011
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Bun Kobayashi, Liyang Zhang, Mau-Chung Frank Chang, Pei-Ming Daniel Chow
  • Publication number: 20110018624
    Abstract: An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit for generating a power control voltage having a voltage characteristic that offsets temperature characteristics of the received RF signal. The amplifier circuit further comprises a power amplifier coupled to the bias circuit. The power amplifier includes a driver stage providing the RF signal. The detection circuit compensates temperature variation of the inputted detection voltage of the received RF signal.
    Type: Application
    Filed: August 2, 2010
    Publication date: January 27, 2011
    Applicant: Silicon Storage Technology, Inc.
    Inventors: Bun Kobayashi, Liyang Zhang, Mau-Chung Frank Chang, Pei-Ming Daniel Chow
  • Patent number: 7852063
    Abstract: An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit for generating a power control voltage having a voltage characteristic that offsets temperature characteristics of the received RF signal. The amplifier circuit further comprises a power amplifier coupled to the bias circuit. The power amplifier includes a driver stage providing the RF signal. The detection circuit compensates temperature variation of the inputted detection voltage of the received RF signal.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: December 14, 2010
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Bun Kobayashi, Liyang Zhang, Mau-Chung Frank Chang, Pei-Ming Daniel Chow
  • Publication number: 20100271136
    Abstract: A front-end module comprises a plurality of chips that includes first and second functional blocks and an interconnection circuit. The first functional block is formed using a first process type and includes a digital control circuit that generates a digital control signal in response to an external control signal from outside the front end module. The second functional block is formed using a second process type and includes a digitally controlled circuit controlled by the digital control signal generated by the first functional block. The second process type is different from the first process type. The interconnection circuit couples the digital control circuit and the digitally controlled circuit to provide the digital control signal to the digitally controlled circuit. In one aspect, the first functional block may be a low noise amplifier formed by a pseudomorphic high electron mobility transistor process.
    Type: Application
    Filed: April 22, 2009
    Publication date: October 28, 2010
    Inventors: Liyang Zhang, Pei-Ming Daniel Chow, Mau-Chung Frank Chang
  • Publication number: 20100134218
    Abstract: An attenuator system comprises an attenuator and a control circuit for controlling the attenuation of the attenuator. In one embodiment, the attenuator comprises two diodes or two diode connected transistors, and the control circuit comprises two transistors as the only active devices. In another embodiment, the control circuit comprises another transistor in a shut down circuit.
    Type: Application
    Filed: December 2, 2008
    Publication date: June 3, 2010
    Inventors: Bun Kobayashi, Steven W. Schell, Pei-Ming Daniel Chow, Mau-Chung Frank Chang
  • Publication number: 20090302830
    Abstract: An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit for generating a power control voltage having a voltage characteristic that offsets temperature characteristics of the received RF signal. The amplifier circuit further comprises a power amplifier coupled to the bias circuit. The power amplifier includes a driver stage providing the RF signal. The detection circuit compensates temperature variation of the inputted detection voltage of the received RF signal.
    Type: Application
    Filed: June 4, 2008
    Publication date: December 10, 2009
    Applicant: Silicon Storage Technology, Inc.
    Inventors: Bun Kobayashi, Liyang Zhang, Mau-Chung Frank Chang, Pei-Ming Daniel Chow
  • Patent number: 7356317
    Abstract: A system or method for a circuit network that receives an RF signal, and where a plurality of switching transistors receive an RF signal output by the circuit network and perform mixing with a local oscillation (LO) signal received on a LO input. An active bias circuit performs active bias of the plurality of switching transistors in a feedback loop provided between the LO input and an output of the plurality of switching transistors.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: April 8, 2008
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Zhiwei Xu, Pei-Ming Daniel Chow, M. Frank Chang