Patents by Inventor PEI-MING HSU

PEI-MING HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240087961
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Ju CHOU, Chih-Chung Chang, Jun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Kao, Chen-Hsuan Liao
  • Patent number: 11923250
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Ju Chou, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Gao, Chen-Hsuan Liao
  • Publication number: 20190318464
    Abstract: A fingerprint identification module test system includes a light source, a projection surface, a low-end image pickup device and a judgment module. The light source emits and projects a light beam onto an under-test fingerprint identification module. After the light beam is reflected by the under-test fingerprint identification module and projected onto the projection surface, a projected image is formed on the projection surface. Then, the low-end image pickup device photographs the projected image to acquire an under-test corresponding to the under-test fingerprint identification module. According to the result of comparing the under-test image with the predetermined image, the judgment module judges whether the under-test fingerprint identification module complies with the production specifications. Since the fingerprint identification module test system uses parity devices to test the under-test fingerprint identification module, the fingerprint identification module test system is cost-effective.
    Type: Application
    Filed: May 25, 2018
    Publication date: October 17, 2019
    Inventors: SHENG-CHI CHAN, JUI-TING CHIEN, PEI-MING HSU