Patents by Inventor Pei Ouyang

Pei Ouyang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FABRICATING TANDEM SOLAR CELL DEVICES USING DEVICE-LEVEL ENCAPSULATION
    Publication number: 20240381675
    Abstract: A method includes obtaining a set of tandem solar cell devices, and forming, on each tandem solar cell device of the set of tandem solar cell devices using a deposition process, a discrete encapsulation layer along an upper surface and side surfaces of the tandem solar cell device.
    Type: Application
    Filed: April 29, 2024
    Publication date: November 14, 2024
    Inventors: Yongkee Chae, Yong Jin Kim, Cheng-Pei Ouyang, Su-Ho Cho
  • FABRICATING SOLAR CELL DEVICES TO REDUCE ACTIVE LAYER DAMAGE
    Publication number: 20240381753
    Abstract: A method includes obtaining a base structure of a tandem solar cell device and forming a transparent conductive oxide (TCO) layer on the base structure using a low damage sputter deposition (LDSD) process. The LDSD process includes a rotary facing sputter deposition process.
    Type: Application
    Filed: April 29, 2024
    Publication date: November 14, 2024
    Inventors: Yongkee Chae, Xun Li, Jun-Nan Liu, Shinobu Abe, Cheng-Pei Ouyang, Su-Ho Cho, Yong Jin Kim, Thomas Werner Zilbauer
  • Race condition detection and expression
    Patent number: 7243319
    Abstract: A method and apparatus for improved race detection and expression is disclosed. The race detection method and apparatus disclosed herein detects races statically by analyzing the circuits, which are usually written in a hardware description language (HDL), such as VHDL or Verilog. Compared with known simulation approaches, the inventive method and apparatus has at least the following advantages: no test vectors are required; all potential races can be detected; and in simulator approaches, if the right test vectors are not provided, then the races cannot be found (the invention avoids this last constraint).
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: July 10, 2007
    Assignee: Cadence Design (Israel) II Ltd.
    Inventor: Pei Ouyang
  • Race condition detection and expression
    Patent number: 7017129
    Abstract: A method and apparatus for improved race detection and expression is disclosed. The race detection method and apparatus disclosed herein detects races statically by analyzing the circuits, which are usually written in a hardware description language (HDL), such as VHDL or Verilog. Compared with known simulation approaches, the inventive method and apparatus has at least the following advantages: no test vectors are required; all potential races can be detected; and in simulator approaches, if the right test vectors are not provided, then the races cannot be found (the invention avoids this last constraint).
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: March 21, 2006
    Assignee: Verisity Design, Inc.
    Inventor: Pei Ouyang
  • Race condition detection and expression
    Publication number: 20050138583
    Abstract: A method and apparatus for improved race detection and expression is disclosed. The race detection method and apparatus disclosed herein detects races statically by analyzing the circuits, which are usually written in a hardware description language (HDL), such as VHDL or Verilog. Compared with known simulation approaches, the inventive method and apparatus has at least the following advantages: no test vectors are required; all potential races can be detected; and in simulator approaches, if the right test vectors are not provided, then the races cannot be found (the invention avoids this last constraint).
    Type: Application
    Filed: November 15, 2004
    Publication date: June 23, 2005
    Inventor: Pei Ouyang
  • Race condition detection and expression
    Publication number: 20030140326
    Abstract: A method and apparatus for improved race detection and expression is disclosed. The race detection method and apparatus disclosed herein detects races statically by analyzing the circuits, which are usually written in a hardware description language (HDL), such as VHDL or Verilog. Compared with known simulation approaches, the inventive method and apparatus has at least the following advantages: no test vectors are required; all potential races can be detected; and in simulator approaches, if the right test vectors are not provided, then the races cannot be found (the invention avoids this last constraint).
    Type: Application
    Filed: February 3, 2003
    Publication date: July 24, 2003
    Inventor: Pei Ouyang
  • Race condition detection and expression
    Patent number: 6536019
    Abstract: A method and apparatus for improved race detection and expression is disclosed. The race detection method and apparatus disclosed herein detects races statically by analyzing the circuits, which are usually written in a hardware description language (HDL), such as VHDL or Verilog. Compared with known simulation approaches, the inventive method and apparatus has at least the following advantages: no test vectors are required; all potential races can be detected; and in simulator approaches, if the right test vectors are not provided, then the races cannot be found (the invention avoids this last constraint).
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: March 18, 2003
    Assignee: Verisity Design, Inc.
    Inventor: Pei Ouyang