Abstract: The present invention provides a method of fabricating a flash memory. The method first involves forming a gate oxide layer on a silicon substrate of a semiconductor wafer. Then, a first polysilicon layer, and a silicon nitride layer are formed, respectively, on the gate oxide layer. A lithographic process is then used to pattern a first photoresist layer for defining a memory array area and a peripheral region. The first photoresist layer is then used to etch the silicon nitride layer down to the surface of the silicon substrate to form a wide gap at the boundary between the memory array area and the peripheral region, and a plurality of gaps in the memory array area. An HDP oxide layer is then deposited, followed by coating of a photoresist (PR) on the wafer to achieve cell planarization. Thereafter, an oxide etch back process is performed followed by stripping of both the PR coating and the silicon nitride layer. Finally, a floating gate and a control gate are formed, respectively.

Abstract: In accordance with the present invention, a method for preventing polysilicon stringers in memory devices is disclosed. The key aspect of the present invention is the formation of a floating gate structure with multi-level oxidation rates the lower portion of the floating gate structure the higher oxidation rate, such as a floating gate structure with two polysilicon layers of different doping concentration or crystallinity the lower polysilicon layer the higher doping concentration, or the lower polysilicon layer the higher crystallinity. Therefore, in a later oxidation process a desired profile of the floating gate structure for etch process defining word lines is formed, that is from lower portion to higher portion of the floating gate structure an increasing width profile is formed. The width of the upper portion of the floating gate structure is bigger than that of the lower portion of the floating gate structure.

Abstract: The present invention provides a high density plasma (HDP) chemical vapor deposition (CVD) chamber. The upper wall of the HDP CVD chamber in the present invention is composed by two ceramic layers with a defaulted distance, so the number and the distribution of the nozzles on the inner layer of the upper wall of the chamber can be adjusted according to desire. In another hand, the material of the upper wall of the chamber in the present invention is ceramic so that can be penetrated by the electromagnetic field created by the inductive coil entwined outside the chamber to generate a region of plasma within the chamber. By the application of the present invention, the time and the costs of installing the nozzles can be saved and the problem of adjusting the nozzles is not need to consider.

Abstract: A fabrication method for a dual damascene structure includes forming a first dielectric layer on a substrate already comprises a first conductive layer formed therein. The first dielectric layer is then patterned to form a via opening, exposing the first conductive layer. After this, a second dielectric layer is formed on the first dielectric layer by hot filament chemical vapor deposition, wherein the second dielectric layer does not fill the via opening. The second dielectric layer is then patterned to form a trench. The trench and the via opening together form a dual damascene opening. A second conductive layer is further filled the damascene opening to complete the fabrication of a dual damascene structure.

Abstract: A method for manufacturing dielectric layers between metal parts by forming fluorine silicate glass by high density plasma deposition using radio frequency power of low bias voltage. The method includes filling in a gap with fluorine silicate glass by high density plasma deposition with slower rate of deposition and radio frequency power of high bias voltage, and then using fluorine silicate glass deposited with fast rate of deposition and radio frequency power of no or low bias voltage as a sacrificial layer, and being made plane by a chemical-mechanic polishing CMP.

Abstract: A method of forming the shallow trench isolation by introducing a nitrogen treatment after the step of forming the trench is disclosed. The exposed pad oxide layer located on the upper portion of the trench is transferred into silicon oxynitride layer. Therefore, the formation of the bird's break and electric influence of the device are avoided. Accordingly, the scale down requirement of the future device is also satisfied.

Abstract: A fabrication method for a dual damascene structure includes forming a first dielectric layer on a substrate already comprises a first conductive layer formed therein. The first dielectric layer is then patterned to form a via opening, exposing the first conductive layer. After this, a second dielectric layer is formed on the first dielectric layer by hot filament chemical vapor deposition, wherein the second dielectric layer does not fill the via opening. The second dielectric layer is then patterned to form a trench. The trench and the via opening together form a dual damascene opening. A second conductive layer is further filled the damascene opening to complete the fabrication of a dual damascene structure.

Abstract: A method for forming a self-aligned mask read only memory by dual damascene trenches is disclosed. In the method, a thickness difference is formed between the gate area and periphery to be formed with a dual damascene trench so as to be formed with a condition of self-alignment of read only memory code. Thus, the manufacturing range in the lithography is enlarged, and an ion implantation process with self-aligned ability complete. Therefore, self-aligned read only memory codes and metal word lines are formed. The defect of disalignment in the read only memory code is resolved and the difficulty in the manufacturing process is reduced.

Abstract: a substrate is provided, and a dielectric layer is formed, thereon. Then a photoresist layer is formed on the dielectric layer and defined a predetermined region for ion implantation. Next, a dense region of dielectric layer is formed by retrograde implantation with photoresist layer as an ion implanted mask, wherein the dense region is a predetermined region for trench. A hard mask layer is formed on the dielectric layer after the photoresist layer is removed. Afterward forming and defining another photoresist layer on the hard mask layer to expose a partial surface of the hard mask layer as a trench region, wherein the partial surface of the hard mask layer comprises the dense region. Subsequently, an etching process is performed by means of the photoresist layer as the etched mask to etch through the hard mask layer and the dielectric layer until the substrate surface is exposed for patterning the dual damascene.

Abstract: A method to planarize a flash memory device, wherein the method is applied on a substrate having a polysilicon layer and a cap layer sequentially formed thereon. Thereafter, the cap layer and the polysilicon layer are patterned to form the peripheral circuit region and the memory cell region. A dielectric layer is then formed on the substrate, covering the cap layer. A portion of the dielectric layer is further removed to expose a part of the cap layer, such that the dielectric layer above the cap layer and the dielectric layer on both sides of the cap layer become separated. A portion of the dielectric layer in the peripheral circuit region is then removed, followed by forming a photoresist layer on the substrate such that a portion of the dielectric layer in the peripheral circuit region and in the memory cell region is exposed. The dielectric layer exposed by the photoresist layer is then removed, followed by removing the photoresist layer.

Abstract: A method to planarize a flash memory device, wherein the method is applied on a substrate having a polysilicon layer and a cap layer sequentially formed thereon. Thereafter, the cap layer and the polysilicon layer are patterned to form the peripheral circuit region and the memory cell region. A dielectric layer is then formed on the substrate, covering the cap layer. A portion of the dielectric layer is further removed to expose a part of the cap layer, such that the dielectric layer above the cap layer and the dielectric layer on both sides of the cap layer become separated. A portion of the dielectric layer in the peripheral circuit region is then removed, followed by removing the cap layer, wherein the dielectric layer above the cap layer is concurrently removed to complete the planazation of the flash memory device.

Abstract: A substrate is provided, and a first dielectric layer is formed, thereon. Then a first photoresist layer is formed and defined on the first dielectric layer. Next, a dense region as an etched barrier layer is formed in the first dielectric layer by an ion implantation with photoresist layer as a mask. A second dielectric layer is formed on the first dielectric layer after the first photoresist layer is removed. Afterward forming a second photoresist layer on the second dielectric layer and defining a predetermined trench region to expose a partial surface of the second dielectric layer, wherein the partial surface of the second dielectric layer comprises the dense region. Subsequently, an etching process is performed by means of the second photoresist layer as an etched mask to etch through the second dielectric layer and the first dielectric layer until the substrate surface is exposed for patterning the dual damascene.

Abstract: A method of forming the shallow trench isolation by introducing a silicon nitride etching back step and a nitrogen treatment after the step of forming the trench is disclosed. The exposed pad oxide layer located on the upper portion of the trench is transferred into silicon oxynitride layer. Therefore, the formation of the bird's break and electric influence of the device are avoided. Accordingly, the scale down requirement of the future device is also satisfied.

Abstract: A method for forming a high-RI dielectric liner layer to prevent out diffusion of fluorine substances in an intermetal dielectric (IMD) layer of an semiconductor device is provided. The method comprises following steps. First, a patterned conductive layer is deposited on a substrate. Then, a dielectric liner layer is formed by high density plasma enhanced chemical vapor deposition method or plasma enhanced chemical vapor deposition method. The dielectric liner layer is silicon dioxide and has a high-RI between about 1.5 to 1.8. Next, a fluorinated silicate glass layer is deposited on the dielectric liner layer. The high-RI dielectric liner layer is used to reduce out diffusion of fluorine substances in the fluorinated silicate glass layer. Last, it is proceeded a chemical mechanism polishing process to remove additional fluorinated silicate glass layer and the dielectric liner layer.

Abstract: A method for forming shallow trench isolation is disclosed. A pad oxide layer is formed on a substrate, and a mask layer is deposited on the pad oxide layer. The mask layer and the pad oxide layer are patterned to expose the substrate. Thereafter, the exposed substrate is subsequently etched to form a shallow trench. A lining oxide layer is formed by thermal oxidation on the shallow trench sidewalls. Afterwards, a silicon-rich oxide layer is deposited by high-density chemical vapor deposition (HDPCVD) process on the substrate and the shallow trench. Next, a silicon oxide layer is formed using the same HDPCVD process on the silicon-rich layer. Subsequently, an excess portion of silicon oxide and the silicon-rich oxide over the silicon nitride layer are effectively removed using some standard semiconductor processes. Eventually, the mask layer is removed and the pad oxide layer is stripped to form silicon oxide plug served as shallow trench isolation.

Abstract: A method of fabricating self-aligned multilevel mask read only memory (ROM). The method can improve the process window to reduce process difficulty by utilizing the self-aligned implantation. Moreover, by utilizing the connection between the word line and the gate and implantation of the ROM code with self-aligned implatiation to increase the difference between the threshold voltages of different gates, and therefore, multilevel cell transistors with for the mask ROM with multilevel threshold voltages are formed to times the capacity of the mask ROM.

Abstract: A method of fabricating self-aligned multilevel mask read only memory (ROM). The method can improve the process window to reduce process difficulty by utilizing the self-aligned implantation. Moreover, by utilizing the height difference between different gate polysilicon layers and implantation of the ROM code with self-aligned implatiation to increase the difference between the threshold voltages of different gates, and therefore, multilevel cell transistors with for the mask ROM with multilevel threshold voltages are formed to times the capacity of the mask ROM.

Abstract: A method for forming a barrier layer on a semiconductor substrate for the fabrication of a conductive layer of copper is disclosed. A double film of titanium and titanium nitride (Ti/TiN) is employed to serve as barrier layer. The titanium layer is formed by two-stage ionized metal plasma (IMP) sputtering. A wafer bias is provided at the first stage to get excellent bottom step coverage. No wafer bias is added at the second stage, and (002)-oriented texture of titanium is constructed. Over such a titanium liner structure, the titanium nitride barrier layer is formed with (111)-oriented texture. Finally, the copper layer is formed on the titanium nitride layer with (111) crystallographic orientation.

Abstract: A method to planarize a flash memory device, wherein the method is applied on a substrate having a polysilicon layer and a cap layer sequentially formed thereon. Thereafter, the cap layer and the polysilicon layer are patterned to form the peripheral circuit region and the memory cell region. A dielectric layer is then formed on the substrate, covering the cap layer. A portion of the dielectric layer is further removed to expose a part of the cap layer, such that the dielectric layer above the cap layer and the dielectric layer on both sides of the cap layer become separated. A portion of the dielectric layer in the peripheral circuit region is then removed, followed by removing the cap layer, wherein the dielectric layer above the cap layer is concurrently removed to complete the planazation of the flash memory device.

Abstract: A method for improving the electrical property of gate in polycide structure is disclosed. First, a gate oxide layer is formed on the surface of the silicon substrate. The following procedure acts as one of the key points for the invention comprising the process steps of (1) forming a highly-doped polysilicon layer on the gate oxide, (2) forming an undoped amorphous silicon layer on the polysilicon layer, and followed by (3) forming a tungsten silicon layer on the amorphous silicon. Next, annealing at high temperature and in short time is performed. Such a stacked gate structure has low resistance and can solve the following problems: (1)peeling of tungsten silicide after annealing, (2) degradation of the electrical property of gate due to the diffusing and penetration of fluorine atoms coming from tungsten silicide.