Abstract: A method of forming a semiconductor structure includes forming a semiconductor layer and a metal layer on a first dielectric layer on a semiconductor substrate in sequence; forming a second dielectric layer on a portion of the metal layer; forming a BPSG layer on the second dielectric layer; etching the metal layer and the semiconductor layer; forming a first spacer layer on sidewalls of the semiconductor layer, the metal layer, and the second dielectric layer, and a top surface of the BPSG layer; etching the first spacer layer to expose the BPSG layer; removing the BPSG layer to expose a top surface of the second dielectric layer; forming a second spacer layer on a sidewall of the first spacer layer and the top surface of the second dielectric layer; and etching the second spacer layer to expose the top surface of the second dielectric layer.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a bit line structure over the substrate; forming a spacer surrounding the bit line structure; forming a polysilicon layer covering the bit line structure and the spacer; performing a first etching operation on the polysilicon layer to obtain a first height of the polysilicon layer, wherein the first height is less than a height of the bit line structure or a height of the spacer; performing a second etching operation on a first portion of the spacer; and performing a third etching operation on the polysilicon layer to obtain a second height of the polysilicon layer, wherein the second height is less than the first height.

Abstract: The present disclosure provides a semiconductor structure having a bit line with a tapered configuration. The semiconductor structure includes: a substrate; a bit line structure, disposed over the substrate, wherein the bit line structure includes a cylindrical portion and a step portion above the cylindrical portion; a polysilicon layer, disposed over the substrate and around the bit line structure; and a landing pad, disposed over the polysilicon layer and the step portion.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a bit line structure over the substrate; forming a spacer surrounding the bit line structure; forming a polysilicon layer covering the bit line structure and the spacer; performing a first etching operation on the polysilicon layer to obtain a first height of the polysilicon layer, wherein the first height is less than a height of the bit line structure or a height of the spacer; performing a second etching operation on a first portion of the spacer; and performing a third etching operation on the polysilicon layer to obtain a second height of the polysilicon layer, wherein the second height is less than the first height.

Abstract: The present disclosure provides a semiconductor structure having a bit line with a tapered configuration. The semiconductor structure includes: a substrate; a bit line structure, disposed over the substrate, wherein the bit line structure includes a cylindrical portion and a step portion above the cylindrical portion; a polysilicon layer, disposed over the substrate and around the bit line structure; and a landing pad, disposed over the polysilicon layer and the step portion.