Patents by Inventor Pei-Shan Chien
Pei-Shan Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9263277Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a semiconductor device comprises a substrate comprising an isolation region separating and surrounding both a P-active region and an N-active region; a P-work function metal layer in a P-gate structure over the P-active region, wherein the P-work function metal layer comprises a first bottom portion and first sidewalls, wherein the first bottom portion comprises a first layer of metallic compound with a first thickness; and an N-work function metal layer in an N-gate structure over the N-active region, wherein the N-work function metal layer comprises a second bottom portion and second sidewalls, wherein the second bottom portion comprises a second layer of the metallic compound with a second thickness less than the first thickness.Type: GrantFiled: August 30, 2012Date of Patent: February 16, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Shan Chien, Andrew Joseph Kelly
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Patent number: 9240484Abstract: A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.Type: GrantFiled: May 4, 2015Date of Patent: January 19, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Andrew Joseph Kelly, Yasutoshi Okuno, Pei-Shan Chien, Wei-Hsiung Tseng
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Patent number: 9166010Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.Type: GrantFiled: May 11, 2015Date of Patent: October 20, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng
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Publication number: 20150243745Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.Type: ApplicationFiled: May 11, 2015Publication date: August 27, 2015Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng
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Publication number: 20150236160Abstract: A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.Type: ApplicationFiled: May 4, 2015Publication date: August 20, 2015Inventors: Andrew Joseph Kelly, Yasutoshi Okuno, Pei-Shan Chien, Wei-Hsiung Tseng
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Patent number: 9054213Abstract: A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.Type: GrantFiled: September 30, 2014Date of Patent: June 9, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Andrew Joseph Kelly, Yasutoshi Okuno, Pei-Shan Chien, Wei-Hsiung Tseng
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Patent number: 9029930Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.Type: GrantFiled: March 21, 2014Date of Patent: May 12, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng
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Publication number: 20150056774Abstract: A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.Type: ApplicationFiled: September 30, 2014Publication date: February 26, 2015Inventors: Andrew Joseph Kelly, Yasutoshi Okuno, Pei-Shan Chien, Wei-Hsiung Tseng
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Patent number: 8901665Abstract: The present disclosure provides a method of semiconductor fabrication including forming an inter-layer dielectric (ILD) layer on a semiconductor substrate. The ILD layer has an opening defined by sidewalls of the ILD layer. A spacer element is formed on the sidewalls of the ILD layer. A gate structure is formed in the opening adjacent the spacer element. In an embodiment, the sidewall spacer also for a decrease in the dimensions (e.g., length) of the gate structure formed in the opening.Type: GrantFiled: December 22, 2011Date of Patent: December 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Andrew Joseph Kelly, Pei-Shan Chien, Yung-Ta Li, Chan Syun Yang
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Patent number: 8872284Abstract: A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.Type: GrantFiled: March 20, 2012Date of Patent: October 28, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Andrew Joseph Kelly, Yasutoshi Okuno, Pei-Shan Chien, Wei-Hsiung Tseng
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Publication number: 20140203338Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.Type: ApplicationFiled: March 21, 2014Publication date: July 24, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng
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Patent number: 8703556Abstract: A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate and fin structures on the substrate. A sidewall spacer is formed along sidewall of fin structures in the precursor. A portion of fin structure is recessed to form a recessing trench with the sidewall spacer as its upper portion. A semiconductor is epitaxially grown in the recessing trench and continually grown above the recessing trench to form an epitaxial structure.Type: GrantFiled: August 30, 2012Date of Patent: April 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng
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Publication number: 20140061811Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a semiconductor device comprises a substrate comprising an isolation region separating and surrounding both a P-active region and an N-active region; a P-work function metal layer in a P-gate structure over the P-active region, wherein the P-work function metal layer comprises a first bottom portion and first sidewalls, wherein the first bottom portion comprises a first layer of metallic compound with a first thickness; and an N-work function metal layer in an N-gate structure over the N-active region, wherein the N-work function metal layer comprises a second bottom portion and second sidewalls, wherein the second bottom portion comprises a second layer of the metallic compound with a second thickness less than the first thickness.Type: ApplicationFiled: August 30, 2012Publication date: March 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Shan Chien, Andrew Joseph Kelly
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Publication number: 20130249019Abstract: A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.Type: ApplicationFiled: March 20, 2012Publication date: September 26, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Andrew Joseph Kelly, Yasutoshi Okuno, Pei-Shan Chien, Wei-Hsiung Tseng
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Publication number: 20130161762Abstract: The present disclosure provides a method of semiconductor fabrication including forming an inter-layer dielectric (ILD) layer on a semiconductor substrate. The ILD layer has an opening defined by sidewalls of the ILD layer. A spacer element is formed on the sidewalls of the ILD layer. A gate structure is formed in the opening adjacent the spacer element. In an embodiment, the sidewall spacer also for a decrease in the dimensions (e.g., length) of the gate structure formed in the opening.Type: ApplicationFiled: December 22, 2011Publication date: June 27, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")Inventors: Andrew Joseph Kelly, Pei-Shan Chien, Yung-Ta Li, Chan Syun Yang
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Patent number: RE48942Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.Type: GrantFiled: June 30, 2017Date of Patent: February 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng