Patents by Inventor Pei-Shan Tseng

Pei-Shan Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9899369
    Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: February 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pei-Shan Tseng, Yu-Cheng Liao, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
  • Publication number: 20170084604
    Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.
    Type: Application
    Filed: September 22, 2015
    Publication date: March 23, 2017
    Inventors: Pei-Shan Tseng, Yu-Cheng Liao, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
  • Patent number: 8981521
    Abstract: Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: March 17, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Tzu Wang, Pei-Shan Tseng, Tien-Hao Tang
  • Publication number: 20150054132
    Abstract: Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 26, 2015
    Applicant: United Microelectronics Corp.
    Inventors: Chang-Tzu Wang, Pei-Shan Tseng, Tien-Hao Tang