Patents by Inventor Pei-Shiang Chen
Pei-Shiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9336986Abstract: The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.Type: GrantFiled: September 19, 2014Date of Patent: May 10, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chun Wang, Pei-Shiang Chen, Tzu-Chin Lin, Faruk Krecinic, Jeng-Horng Chen, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 9305799Abstract: The present disclosure provides a method for electron-beam (e-beam) lithography patterning. The method includes forming a resist layer on a substrate; performing a first e-beam exposure process to the resist layer according to a first pattern; performing a second e-beam exposure process to the resist layer according to a second pattern, wherein the second patterned is overlapped to the first pattern on the resist layer; and developing the resist layer.Type: GrantFiled: September 4, 2014Date of Patent: April 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Shiang Chen, Hung-Chun Wang, Jeng-Horng Chen
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Patent number: 8945803Abstract: The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.Type: GrantFiled: December 16, 2013Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Shiang Chen, Hung-Chun Wang, Jeng-Horng Chen, Cheng-Hung Chen, Shih-Chi Wang, Nian-Fuh Cheng, Chia-Chi Lin
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Publication number: 20150008343Abstract: The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.Type: ApplicationFiled: September 19, 2014Publication date: January 8, 2015Inventors: HUNG-CHUN WANG, PEI-SHIANG CHEN, TZU-CHIN LIN, FARUK KRECINIC, JENG-HORNG CHEN, WEN-CHUN HUANG, RU-GUN LIU
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Publication number: 20140367588Abstract: The present disclosure provides a method for electron-beam (e-beam) lithography patterning. The method includes forming a resist layer on a substrate; performing a first e-beam exposure process to the resist layer according to a first pattern; performing a second e-beam exposure process to the resist layer according to a second pattern, wherein the second patterned is overlapped to the first pattern on the resist layer; and developing the resist layer.Type: ApplicationFiled: September 4, 2014Publication date: December 18, 2014Inventors: Pei-Shiang Chen, HUNG-CHUN WANG, JENG-HORNG CHEN
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Patent number: 8877410Abstract: The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.Type: GrantFiled: October 1, 2013Date of Patent: November 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chen, Pei-Shiang Chen, Shih-Chi Wang, Jeng-Horng Chen
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Patent number: 8841049Abstract: The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.Type: GrantFiled: August 12, 2013Date of Patent: September 23, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chun Wang, Pei-Shiang Chen, Tzu-Chin Lin, Faruk Krecinic, Jeng-Horng Chen, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 8835082Abstract: The present disclosure provides a method for electron-beam (e-beam) lithography patterning. The method includes forming a resist layer on a substrate; performing a first e-beam exposure process to the resist layer according to a first pattern; performing a second e-beam exposure process to the resist layer according to a second pattern, wherein the second patterned is overlapped to the first pattern on the resist layer; and developing the resist layer.Type: GrantFiled: July 31, 2012Date of Patent: September 16, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Shiang Chen, Hung-Chun Wang, Jeng-Horng Chen
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Publication number: 20140099582Abstract: The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.Type: ApplicationFiled: December 16, 2013Publication date: April 10, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Shiang Chen, Hung-Chun Wang, Jeng-Horng Chen, Cheng-Hung Chen, Shih-Chi Wang, Nian-Fuh Cheng, Chia-Chi Lin
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Publication number: 20140038107Abstract: The present disclosure provides a method for electron-beam (e-beam) lithography patterning. The method includes forming a resist layer on a substrate; performing a first e-beam exposure process to the resist layer according to a first pattern; performing a second e-beam exposure process to the resist layer according to a second pattern, wherein the second patterned is overlapped to the first pattern on the resist layer; and developing the resist layer.Type: ApplicationFiled: July 31, 2012Publication date: February 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Shiang Chen, Hung-Chun Wang, Jeng-Horng Chen
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Publication number: 20140023972Abstract: The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.Type: ApplicationFiled: October 1, 2013Publication date: January 23, 2014Inventors: Cheng-Hung Chen, Pei-Shiang Chen, Shih-Chi Wang, Jeng-Horng Chen
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Patent number: 8609308Abstract: The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.Type: GrantFiled: May 31, 2012Date of Patent: December 17, 2013Assignee: Taiwan Semicondcutor Manufacturing Company, Ltd.Inventors: Pei-Shiang Chen, Hung-Chun Wang, Jeng-Horng Chen, Cheng-Hung Chen, Shih-Chi Wang, Nian-Fuh Cheng, Chia-Chi Lin
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Publication number: 20130323648Abstract: The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.Type: ApplicationFiled: May 31, 2012Publication date: December 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Shiang Chen, Hung-Chun Wang, Jeng-Horng Chen, Cheng-Hung Chen, Shih-Chi Wang, Nian-Fuh Cheng, Chia-Chi Lin
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Patent number: 8601407Abstract: Provided is a method of performing a maskless lithography process. The method includes providing a proximity correction pattern. The method includes generating a deformed pattern based on the proximity correction pattern. The method includes performing a first convolution process to the proximity correction pattern to generate a first proximity correction pattern contour. The method includes processing the first proximity correction pattern contour to generate a second proximity correction pattern contour. The method includes performing a second convolution process to the deformed pattern to generate a first deformed pattern contour. The method includes processing the first deformed pattern contour to generate a second deformed pattern contour. The method includes identifying mismatches between the second proximity correction pattern contour and the second deformed pattern contour. The method includes determining whether the deformed pattern is lithography-ready in response to the identifying.Type: GrantFiled: August 25, 2011Date of Patent: December 3, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chun Wang, Pei-Shiang Chen, Tzu-Chin Lin, Cheng-Hung Chen, Shih-Chi Wang, Nian-Fuh Cheng, Jeng-Horng Chen, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20130316289Abstract: The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.Type: ApplicationFiled: August 12, 2013Publication date: November 28, 2013Applicant: Taiwan Seminconductor Manufacturing Company, Ltd.Inventors: Hung-Chun Wang, Pei-Shiang Chen, Tzu-Chin Lin, Faruk Krecinic, Jeng-Horng Chen, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 8563224Abstract: The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.Type: GrantFiled: June 4, 2012Date of Patent: October 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chen, Pei-Shiang Chen, Shih-Chi Wang, Jeng-Horng Chen
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Patent number: 8507159Abstract: The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.Type: GrantFiled: March 16, 2011Date of Patent: August 13, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chun Wang, Pei-Shiang Chen, Tzu-Chin Lin, Faruk Krecinic, Jeng-Horng Chen, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20130055173Abstract: The present disclosure involves a method of performing a maskless lithography process. The method includes providing a proximity correction pattern. The method includes generating a deformed pattern based on the proximity correction pattern. The method includes performing a first convolution process to the proximity correction pattern to generate a first proximity correction pattern contour. The method includes processing the first proximity correction pattern contour to generate a second proximity correction pattern contour. The method includes performing a second convolution process to the deformed pattern to generate a first deformed pattern contour. The method includes processing the first deformed pattern contour to generate a second deformed pattern contour. The method includes identifying mismatches between the second proximity correction pattern contour and the second deformed pattern contour.Type: ApplicationFiled: August 25, 2011Publication date: February 28, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chun Wang, Pei-Shiang Chen, Tzu-Chin Lin, Cheng-Hung Chen, Shih-Chi Wang, Nian-Fuh Cheng, Jeng-Horng Chen, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20120237877Abstract: The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.Type: ApplicationFiled: March 16, 2011Publication date: September 20, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chun Wang, Pei-Shiang Chen, Tzu-Chin Lin, Faruk Krecinic, Jeng-Horng Chen, Wen-Chun Huang, Ru-Gun Liu