Abstract: A power amplifying circuit includes a switching circuit, an amplifier and a load. The switching circuit receives a first supply voltage and a second supply voltage. When the switching circuit is in a first operation mode, the first supply voltage is provided to a node. When the switching circuit is in a second operation mode, the second supply voltage is provided to the node. The amplifier receives a first input signal and a second input signal, and outputs a first output signal and a second output signal from a first output terminal and a second output signal, respectively. The load includes a first inductor and a second inductor. The first inductor is connected between the node and the first output terminal. The second inductor is connected between the node and the second output terminal.

Abstract: The present invention discloses a multi-channel timing recovery device capable of generating a common clock for processing a plurality of data channel signals, comprising: a first channel timing recovery circuit, and a second channel timing recovery circuit. The said first channel timing recovery circuit includes a first detecting circuit capable of detecting phase and/or frequency, an oscillation control circuit, an oscillator and a feedback circuit, and is operable to generate the common clock according to a first channel signal which could be a clock signal or a data signal. The said second channel timing recovery circuit includes a second phase detecting circuit, a second phase control circuit and a second clock output circuit, and is operable to generate a second clock according to the common clock and determine the phase of the second clock according to a second channel signal which is a data signal.

Abstract: The present invention discloses a multi-channel timing recovery device capable of generating a common clock for processing a plurality of data channel signals, comprising: a first channel timing recovery circuit, and a second channel timing recovery circuit. The said first channel timing recovery circuit includes a first detecting circuit capable of detecting phase and/or frequency, an oscillation control circuit, an oscillator and a feedback circuit, and is operable to generate the common clock according to a first channel signal which could be a clock signal or a data signal. The said second channel timing recovery circuit includes a second phase detecting circuit, a second phase control circuit and a second clock output circuit, and is operable to generate a second clock according to the common clock and determine the phase of the second clock according to a second channel signal which is a data signal.

Abstract: A clock data recovery method samples an input signal according to a reference clock to generate a plurality of sampling results. A first and a second sampling clocks are generated according to the reference clock. A phase difference between the two sampling clocks is larger than zero and less than half an UI and each UI corresponds to an input data. Successive UIs of the input signal are sampled according to the first and the second sampling clocks to generate a first and a second sampling results in each UI. The two sampling results are compared to generate a comparison result. An adjusting signal is generated according to the comparison result and the input data. The first and the second sampling clocks are adjusted according to the adjusting signal such that the sampling results of each UI substantially correspond to a peak value at the UI of the input signal.

Abstract: An equalizer includes a first sampler, a second sampler, and an equalization circuit. The first sampler is used for sampling an input data to generate an output data, and the second sampler is used for sampling the input data to generate an edge information. The equalization circuit is coupled to the first sampler and the second sampler, and includes an equalization unit and a control unit. The equalization unit performs an equalization operation on an original input data in order to generate the input data according to a plurality of tap coefficients. The control unit is coupled to the equalization unit, for adjusting the plurality of tap coefficients according to the output data and the edge information.

Abstract: A clock data recovery method samples an input signal according to a reference clock to generate a plurality of sampling results. A first and a second sampling clocks are generated according to the reference clock. A phase difference between the two sampling clocks is larger than zero and less than half an UI and each UI corresponds to an input data. Successive UIs of the input signal are sampled according to the first and the second sampling clocks to generate a first and a second sampling results in each UI. The two sampling results are compared to generate a comparison result. An adjusting signal is generated according to the comparison result and the input data. The first and the second sampling clocks are adjusted according to the adjusting signal such that the sampling results of each UI substantially correspond to a peak value at the UI of the input signal.

Abstract: A method and device of the power saving for transmitting a signal is provided. The method comprises the steps of: transmitting a test signal with a first test amplitude from a local terminal, wherein the first test amplitude is selected from a plurality of preset amplitudes; acknowledging that the test signal with the first test amplitude has been received by a remote terminal if an acknowledgement signal is transmitted from the remote terminal for a response to the test signal; and transmitting a data signal having a data amplitude based on the first test amplitude. The device can transmit the data signal with a small data signal amplitude by the method to achieve the saving power.

Abstract: A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery circuit, thereby to test the jitter tolerance of the clock and data recovery circuit. Accordingly, IC test cost is significantly reduced by increasing few circuit sizes.

Abstract: A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery circuit, thereby to test the jitter tolerance of the clock and data recovery circuit. Accordingly, IC test cost is significantly reduced by increasing few circuit sizes.

Abstract: A clock and data recovery device, a sampler and a sampling method thereof are provided. The sampler includes a phase generation circuit and a first edge sampling circuit electrically connected with the phase generation circuit. The phase generation circuit is configured to generate a plurality of first phases which have different phase values. The first edge sampling circuit is configured to sample a plurality of first edge values of a plurality of bits of a data signal according to the first phases so that the clock and data recovery device determines a clock of the data signal according to the first edge values.

Abstract: A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery circuit, thereby to test the jitter tolerance of the clock and data recovery circuit. Accordingly, IC test cost is significantly reduced by increasing few circuit sizes.

Abstract: An apparatus and method for clock regeneration with low jitter. The method includes the following steps: (a) using a phase lock loop to generate a first clock that is phase locked to a reference clock; (b) using a binary phase detector for generating a phase error signal by detecting a timing difference between the input signal and a second clock; (c) filtering the phase error signal to generate a first control word and a second control word; (d) performing a phase rotation on the first clock by an amount controlled by the first control word to generate the second clock; (e) filtering the second control word to generate a third control word; (f) sampling the third control word to generate a fourth control word using a third clock; and (g) performing a phase rotation on the first clock by an amount controlled by the fourth control word to generate the third clock. Comparable features for performing these steps are provided in the apparatus.

Abstract: An apparatus and method for clock regeneration with low jitter. The method includes the following steps: (a) using a phase lock loop to generate a first clock that is phase locked to a reference clock; (b) using a binary phase detector for generating a phase error signal by detecting a timing difference between the input signal and a second clock; (c) filtering the phase error signal to generate a first control word and a second control word; (d) performing a phase rotation on the first clock by an amount controlled by the first control word to generate the second clock; (e) filtering the second control word to generate a third control word; (f) sampling the third control word to generate a fourth control word using a third clock; and (g) performing a phase rotation on the first clock by an amount controlled by the fourth control word to generate the third clock. Comparable features for performing these steps are provided in the apparatus.

Abstract: A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery circuit, thereby to test the jitter tolerance of the clock and data recovery circuit. Accordingly, IC test cost is significantly reduced by increasing few circuit sizes.

Abstract: A method and device of the power saving for transmitting a signal is provided. The method comprises the steps of: transmitting a test signal with a first test amplitude from a local terminal, wherein the first test amplitude is selected from a plurality of preset amplitudes; acknowledging that the test signal with the first test amplitude has been received by a remote terminal if an acknowledgement signal is transmitted from the remote terminal for a response to the test signal; and transmitting a data signal having a data amplitude based on the first test amplitude. The device can transmit the data signal with a small data signal amplitude by the method to achieve the saving power.

Abstract: A voltage control oscillator and a control method thereof is disclosed in the invention. The voltage control oscillator increases frequency of an output frequency as a control signal is increased under a first mode. The voltage control oscillator decreases frequency of the output frequency as a control signal is increased under a second mode.

Abstract: An equalizer includes a first sampler, a second sampler, and an equalization circuit. The first sampler is used for sampling an input data to generate an output data, and the second sampler is used for sampling the input data to generate an edge information. The equalization circuit is coupled to the first sampler and the second sampler, and includes an equalization unit and a control unit. The equalization unit performs an equalization operation on an original input data in order to generate the input data according to a plurality of tap coefficients. The control unit is coupled to the equalization unit, for adjusting the plurality of tap coefficients according to the output data and the edge information.

Abstract: A phase lock loop device and a control method is disclosed in the present invention. The phase lock loop device includes a phase lock loop circuit and a memory unit. The phase lock loop generates a phase lock clock signal according to a control voltage. The memory unit couples the phase lock loop circuit. The memory unit provides an initial signal to the phase lock loop circuit for recovering the control voltage to a preset value according to a digital value while the phase lock loop circuit is enabled.

Abstract: A microwave or millimeter-wave balun is provided. The balun uses three edge-coupled lines along with a plurality of air bridges instead of two edge-coupled lines used in a conventional planar Marchand balun. The first edge-coupled line and the second edge-coupled line are substantially parallel, and the third edge-coupled line is disposed also substantially in parallel between the first edge-coupled line and the second edge-coupled line. The plurality of air bridges are transmission lines between the first edge-coupled line and the second edge-coupled line. The air bridges have total width longer than one half of the total length of the first edge-coupled line or the second edge-coupled line. By combining three edge-coupled-lines and a plurality of air bridges, the Marchand balun has a higher coupling coefficient and increases the operation bandwidth. The microwave monolithic integrated circuit (MMIC) mixer based on the balun can provide compact size compared to conventional ones.

Abstract: A microwave or millimeter-wave balun is provided. The balun uses three edge-coupled lines along with a plurality of air bridges instead of two edge-coupled lines used in a conventional planar Marchand balun. The first edge-coupled line and the second edge-coupled line are substantially parallel, and the third edge-coupled line is disposed also substantially in parallel between the first edge-coupled line and the second edge-coupled line. The plurality of air bridges are transmission lines between the first edge-coupled line and the second edge-coupled line. The air bridges have total width longer than one half of the total length of the first edge-coupled line or the second edge-coupled line. By combining three edge-coupled-lines and a plurality of air bridges, the Marchand balun has a higher coupling coefficient and increases the operation bandwidth. The microwave monolithic integrated circuit (MMIC) mixer based on the balun can provide compact size compared to conventional ones.