Abstract: A wireless serial connection communication system, including: a first circuit board, including a first antenna module which includes a first front wireless communication terminal and a first rear wireless communication terminal; and a second circuit board, disposed adjacent to the first circuit board, the second circuit board including a second antenna module which includes a second front wireless communication terminal and a second rear wireless communication terminal. The first rear wireless communication terminal is face to face adjacent to the second front wireless communication terminal. The first front wireless communication terminal and the second rear wireless communication terminal are respectively disposed on farther sides over the first and second circuit boards, with reference to the first rear wireless communication terminal and the second front wireless communication terminal.

Abstract: A switch control unit and optical control unit, including: a digital-to-analog converter, being switchable between being coupled to a first sensing unit and being coupled to a drive unit, through a common contact pad; a sensing contact pad, coupled to a second sensing unit; an analog-to-digital converter, for sensing voltages at the contact pads when coupled to the sensing units, wherein each of the sensing units has a minimum working voltage level; and a loop switching unit, coupled between the common contact pad, the analog-to-digital converter, and the sensing contact pad, wherein when the voltage at the common contact pad is substantially higher than the minimum working voltage level, the loop switching unit conducts the common contact pad to the analog-to-digital converter to sense the voltage at the common contact pad, and the digital-to-analog converter enters a high-impedance state such that the digital-to-analog converter does not sense the voltage at the common contact pad.

Abstract: The invention provides a wireless communication identification system, including: a master wireless communication unit, sending a first wireless signal, and progressively limiting a count of remaining wireless communication units responding to the first wireless signal in the wireless communication identification system according to a signal level adjustment scenario; and a first wireless communication unit, being the last wireless communication unit in the remaining wireless communication units to respond to the first wireless signal under the signal level adjustment scenario; wherein a first wireless signal connection is established between the master wireless communication unit and the first wireless communication unit by the first wireless signal, and the wireless communication identification system transmits first unit identity information of the first wireless communication unit through the first wireless signal connection.

Abstract: A distributed battery management system, for managing a plurality of battery management units, wherein each of the battery management units, includes: a first battery cell, forming a charge-discharge connection at least with a second battery cell in a second battery management unit; a monitor circuit, monitoring a discharge process of the first battery cell via the charge-discharge connection, to record a discharge voltage time history of the first battery cell; and a calculation unit, calculating a real-time maximal energy storage capacity of the first battery cell, by an electrochemical equation calculated based on the discharge voltage time history and an electrical current time history of the first battery cell during the discharge process. The history of the real-time maximal energy storage capacity of the battery cell may be stored as an identity resume of the battery cell, in a battery resume record device.

Abstract: A switch control unit and optical control unit, including: a digital-to-analog converter, being switchable between being coupled to a first sensing unit and being coupled to a drive unit, through a common contact pad; a sensing contact pad, coupled to a second sensing unit; an analog-to-digital converter, for sensing voltages at the contact pads when coupled to the sensing units, wherein each of the sensing units has a minimum working voltage level; and a loop switching unit, coupled between the common contact pad, the analog-to-digital converter, and the sensing contact pad, wherein when the voltage at the common contact pad is substantially higher than the minimum working voltage level, the loop switching unit conducts the common contact pad to the analog-to-digital converter to sense the voltage at the common contact pad, and the digital-to-analog converter enters a high-impedance state such that the digital-to-analog converter does not sense the voltage at the common contact pad.

Abstract: The present invention provides a differential signal offset adjustment circuit, wherein first and second transistors are respectively coupled between a power supply line and a first current source, and between the power supply line and a second current source. First and second resistors are respectively coupled between the first transistor and a first variable current source, and between the second transistor and a second variable current source. Third and fourth transistors are respectively coupled between a third resistor and a third current source, and between a fourth resistor and a fourth current source, and have input terminals respectively coupled to the first and second resistors. Fifth and sixth transistors are respectively coupled between the power supply line and a fifth current source, and between the power supply line and a sixth current source, and have input terminals respectively coupled to the third and fourth transistors.

Abstract: During frequency detection, a constant current source outputs an output current to charge a variable capacitor for multi-period. In a calibration mode, according to a comparison result between a cross voltage of the variable capacitor and a reference voltage, a capacitance value of the variable capacitor is adjusted. In a monitor mode, according to a reference frequency and the cross voltage of the variable capacitor, a frequency under test of a circuit under test is detected.

Abstract: When digital input data disappear temporarily, within a counting period of the counter and pulse generator, an output voltage of the voltage generator rises, a threshold detector compares the output voltage of the voltage generator with a plurality of threshold values to generate a plurality of comparison results, and a logic gate unit generates a control signal according to the comparison results, to a charge pump, so that the charge pump controls the voltage-controlled oscillator to accelerate or decelerate.

Abstract: When digital input data disappear temporarily, within a counting period of the counter and pulse generator, an output voltage of the voltage generator rises, a threshold detector compares the output voltage of the voltage generator with a plurality of threshold values to generate a plurality of comparison results, and a logic gate unit generates a control signal according to the comparison results, to a charge pump, so that the charge pump controls the voltage-controlled oscillator to accelerate or decelerate.

Abstract: The present invention provides a differential signal offset adjustment circuit, wherein first and second transistors are respectively coupled between a power supply line and a first current source, and between the power supply line and a second current source. First and second resistors are respectively coupled between the first transistor and a first variable current source, and between the second transistor and a second variable current source. Third and fourth transistors are respectively coupled between a third resistor and a third current source, and between a fourth resistor and a fourth current source, and have input terminals respectively coupled to the first and second resistors. Fifth and sixth transistors are respectively coupled between the power supply line and a fifth current source, and between the power supply line and a sixth current source, and have input terminals respectively coupled to the third and fourth transistors.

Abstract: During frequency detection, a constant current source outputs an output current to charge a variable capacitor for multi-period. In a calibration mode, according to a comparison result between a cross voltage of the variable capacitor and a reference voltage, a capacitance value of the variable capacitor is adjusted. In a monitor mode, according to a reference frequency and the cross voltage of the variable capacitor, a frequency under test of a circuit under test is detected.

Abstract: The present invention presents a DC bias circuit including a first biasing circuit and a second biasing circuit. The first biasing circuit includes a first biasing transistor and a first biasing resistor for providing a first bias voltage to an output transistor of the mixer circuit. The first biasing transistor and the output transistor are the same type of transistor and have equal channel lengths. The second biasing circuit includes a second biasing transistor and a second biasing resistor for providing a second bias voltage to an input transistor of the common gate amplifier circuit. The second biasing transistor and the input transistor are the same type of transistor and have equal channel lengths. When the input transistor and the output transistor all operate in a saturation region, alternating current signals output from the mixer circuit is unrelated to a threshold voltage of the output transistor.

Abstract: The present invention presents a DC bias circuit including a first biasing circuit and a second biasing circuit. The first biasing circuit includes a first biasing transistor and a first biasing resistor for providing a first bias voltage to an output transistor of the mixer circuit. The first biasing transistor and the output transistor are the same type of transistor and have equal channel lengths. The second biasing circuit includes a second biasing transistor and a second biasing resistor for providing a second bias voltage to an input transistor of the common gate amplifier circuit. The second biasing transistor and the input transistor are the same type of transistor and have equal channel lengths. When the input transistor and the output transistor all operate in a saturation region, alternating current signals output from the mixer circuit is unrelated to a threshold voltage of the output transistor.

Abstract: The present invention presents a RF receiver circuit including an inductor-coupling single-ended input differential-output LNA, a mixer circuit, and a differential trans-impedance amplifier. The inductor-coupling single-ended input differential-output LNA includes a single-ended input, a balance-to-unbalance transformer, and an inductor-less differential LNA. The balance-to-unbalance transformer is used to transform the radio frequency signals into a plurality of differential-output first differential signals and includes a first inductor and a second inductor.

Abstract: A frequency detection circuit includes a filter, a power detector and a voltage comparator. The filter receives and filters a converted signal to generate a filtered signal. The power of the filtered signal relates to a frequency of the converted signal. The power detector generates a voltage according to the power of the filtered signal. The voltage comparator compares the voltage with multiple reference voltages to generate multiple comparison results. At least one of the inductance and capacitance of an LC tank in an amplifier is adjusted according to the comparison results.

Abstract: An IC, a circuitry, and an RF BIST system are provided. The RF BIST system includes a test equipment, a module circuitry, and an IC. The IC is arranged to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, determine a test result by the RF signal, and report the test result to the test equipment, wherein the module circuitry is external to the IC and the test equipment.

Abstract: A frequency detection circuit includes a filter, a power detector and a voltage comparator. The filter receives and filters a converted signal to generate a filtered signal. The power of the filtered signal relates to a frequency of the converted signal. The power detector generates a voltage according to the power of the filtered signal. The voltage comparator compares the voltage with multiple reference voltages to generate multiple comparison results. At least one of the inductance and capacitance of an LC tank in an amplifier is adjusted according to the comparison results.

Abstract: An IC, a circuitry, and an RF BIST system are provided. The RF BIST system includes a test equipment, a module circuitry, and an IC. The IC is arranged to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, determine a test result by the RF signal, and report the test result to the test equipment, wherein the module circuitry is external to the IC and the test equipment.

Abstract: A processing apparatus for calibrating an analog filter of a communication device in a digital domain is disclosed, wherein the analog filter is arranged to perform a filtering operation upon a communication signal in an analog domain. The processing apparatus includes a signal processing circuit and a digital filter. The signal processing circuit is used for transforming the communication signal between the digital domain and the analog domain. The digital filter is coupled to the signal processing circuit, and used for performing a filtering operation upon the communication signal in the digital domain, wherein a frequency response of the digital filter is arranged to compensate a frequency response of the analog filter according to at least a compensation parameter generated with reference to a frequency-related characteristic of the analog filter.

Abstract: A processing apparatus for calibrating an analog filter of a communication device in a digital domain is disclosed, wherein the analog filter is arranged to perform a filtering operation upon a communication signal in an analog domain. The processing apparatus includes a signal processing circuit and a digital filter. The signal processing circuit is used for transforming the communication signal between the digital domain and the analog domain. The digital filter is coupled to the signal processing circuit, and used for performing a filtering operation upon the communication signal in the digital domain, wherein a frequency response of the digital filter is arranged to compensate a frequency response of the analog filter according to at least a compensation parameter generated with reference to a frequency-related characteristic of the analog filter.