Patents by Inventor PEI-WEI LEE
PEI-WEI LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128231Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are presented. In embodiments the methods of manufacturing include depositing a first bonding layer on a first substrate, wherein the first substrate comprises a semiconductor substrate and a metallization layer. The first bonding layer and the semiconductor substrate are patterned to form first openings. A second substrate is bonded to the first substrate. After the bonding the second substrate, the second substrate is patterned to form second openings, at least one of the second openings exposing at least one of the first openings. After the patterning the second substrate, a third substrate is bonded to the second substrate, and after the bonding the third substrate, the third substrate is patterned to form third openings, at least one of the third openings exposing at least one of the second openings.Type: ApplicationFiled: January 4, 2023Publication date: April 18, 2024Inventors: Fu Wei Liu, Pei-Wei Lee, Yun-Chung Wu, Bo-Yu Chiu, Szu-Hsien Lee, Mirng-Ji Lii
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Publication number: 20240125713Abstract: A method includes directing light at a first side of a semiconductor structure; detecting a first light intensity at a second side of the semiconductor structure, wherein the first light intensity corresponds to the light that penetrated the semiconductor structure from the first side to the second side; and comparing the first light intensity to a second light intensity, wherein the second light intensity corresponds to an expected intensity of light.Type: ApplicationFiled: January 10, 2023Publication date: April 18, 2024Inventors: Hao Chun Yang, Ming-Da Cheng, Pei-Wei Lee, Mirng-Ji Lii
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Publication number: 20240124298Abstract: Microelectromechanical devices and methods of manufacture are presented. Embodiments include bonding a mask substrate to a first microelectromechanical system (MEMS) device. After the bonding has been performed, the mask substrate is patterned. A first conductive pillar is formed within the mask substrate, and a second conductive pillar is formed within the mask substrate, the second conductive pillar having a different height from the first conductive pillar. The mask substrate is then removed.Type: ApplicationFiled: January 10, 2023Publication date: April 18, 2024Inventors: Yun-Chung Wu, Jhao-Yi Wang, Hao Chun Yang, Pei-Wei Lee, Wen-Hsiung Lu
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Publication number: 20240120295Abstract: A semiconductor chip and a manufacturing method thereof are provided. The semiconductor chip includes: an array of pillar structures, disposed on a front surface of the semiconductor chip, and respectively including a ground pillar and multiple working pillars laterally spaced apart from and substantially parallel with a line portion of the ground pillar; and dummy pillar structures, disposed on the front surface of the semiconductor chip and laterally surrounding the pillar structures. Active devices formed inside the semiconductor chip are electrically connected to the working pillar. The ground pillars of the pillar structures and the dummy pillar structures are electrically connected to form a current pathway on the front surface of the semiconductor chip.Type: ApplicationFiled: January 30, 2023Publication date: April 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Hsien Lee, Yun-Chung Wu, Pei-Wei Lee, Fu Wei Liu, Jhao-Yi Wang
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Publication number: 20240120207Abstract: A semiconductor package includes a die having a plurality of devices over a first substrate, where the first substrate includes a dopant at a first concentration and the first substrate has a first width along a horizontal direction. The semiconductor package further includes a second substrate fused with the first substrate, where the second substrate includes the dopant at a second concentration greater than the first concentration.Type: ApplicationFiled: February 15, 2023Publication date: April 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lung-Kai Mao, Wen-Hsiung Lu, Pei-Wei Lee, Szu-Hsien Lee, Chieh-Ning Feng
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Patent number: 11922887Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The diode may be coupled to drive transistor circuitry, a data loading transistor, and emission transistors. The drive transistor circuitry may include at least two transistor portions connected in series. The data loading transistor has a drain region connected to a data line and a source region connected directly to the drive transistor circuitry. The data line may be connected to and overlap the drain region of the data loading transistor. The data line and the source region of the data loading transistor are non-overlapping to reduce row-to-row crosstalk.Type: GrantFiled: July 6, 2021Date of Patent: March 5, 2024Assignee: Apple Inc.Inventors: Shinya Ono, Chin-Wei Lin, Chuan-Jung Lin, Gihoon Choo, Hassan Edrees, Hei Kam, Jung Yen Huang, Pei-En Chang, Rungrot Kitsomboonloha, Szu-Hsien Lee, Zino Lee
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Publication number: 20240047397Abstract: A semiconductor device includes a substrate, one or more wiring layers disposed over the substrate, a passivation layer disposed over the one or more wiring layers, a first conductive layer disposed over the passivation layer, a second conductive layer disposed over the first conductive layer, an isolation structure formed in the first and second conductive layers to isolate a part of the first and second conductive layers, and a first metal pad disposed over the isolation structure and the part of the first and second conductive layers. In one or more of the foregoing or following embodiments, the semiconductor device further includes a second metal pad disposed over the second conductive layer and electrically isolated from the first metal pad.Type: ApplicationFiled: March 20, 2023Publication date: February 8, 2024Inventors: Bo-Yu CHIU, Pei-Wei LEE, Fu Wei LIU, Yun-Chung WU, Hao Chun YANG, Chin-Yu KU, Ming-Da CHENG, Ming-Ji LII
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Publication number: 20240034619Abstract: A method includes forming an interconnect structure over a semiconductor substrate. The interconnect structure includes a plurality of dielectric layers, and the interconnect structure and the semiconductor substrate are in a wafer. A plurality of metal pads are formed over the interconnect structure. A plurality of through-holes are formed to penetrate through the wafer. The plurality of through-holes include top portions penetrating through the interconnect structure, and middle portions underlying and joining to the top portions. The middle portions are wider than respective ones of the top portions. A metal layer is formed to electrically connect to the plurality of metal pads. The metal layer extends into the top portions of the plurality of through-holes.Type: ApplicationFiled: January 9, 2023Publication date: February 1, 2024Inventors: Pei-Wei Lee, Fu Wei Liu, Szu-Hsien Lee, Yun-Chung Wu, Chin-Yu Ku, Ming-Da Cheng, Ming -Ji Lii
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Publication number: 20230387253Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.Type: ApplicationFiled: July 26, 2023Publication date: November 30, 2023Inventors: Tsungyu Hung, Pang-Yen Tsai, Pei-Wei Lee
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Publication number: 20230386925Abstract: A method of fabricating a semiconductor device with superlattice structures on a substrate with an embedded isolation structure is disclosed. The method includes forming an etch stop layer on a substrate, forming a superlattice structure on the etch stop layer, depositing an isolation layer on the superlattice structure, depositing a semiconductor layer on the isolation layer, forming a bi-layer isolation structure on the semiconductor layer, removing the substrate and the etch stop layer, etching the superlattice structure, the isolation layer, the semiconductor layer, and the bi-layer isolation structure to form a fin structure, and forming a gate-all-around structure on the fin structure.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pei-Wei Lee, Pang-Yen Tsai, Tsungyu Hung, Huang-Lin Chao
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Patent number: 11830773Abstract: A method of fabricating a semiconductor device with superlattice structures on a substrate with an embedded isolation structure is disclosed. The method includes forming an etch stop layer on a substrate, forming a superlattice structure on the etch stop layer, depositing an isolation layer on the superlattice structure, depositing a semiconductor layer on the isolation layer, forming a bi-layer isolation structure on the semiconductor layer, removing the substrate and the etch stop layer, etching the superlattice structure, the isolation layer, the semiconductor layer, and the bi-layer isolation structure to form a fin structure, and forming a gate-all-around structure on the fin structure.Type: GrantFiled: August 28, 2020Date of Patent: November 28, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pei-Wei Lee, Pang-Yen Tsai, Tsungyu Hung, Huang-Lin Chao
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Patent number: 11749742Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.Type: GrantFiled: February 23, 2021Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsungyu Hung, Pang-Yen Tsai, Pei-Wei Lee
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Patent number: 11742248Abstract: A method includes etching a hybrid substrate to form a recess in the hybrid substrate, in which the hybrid substrate includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the first semiconductor layer, in which after the etching, a top surface of the first semiconductor layer is exposed to the recess; forming a spacer on a sidewall of the recess, in which the spacer is slanted at a first angle relative to a top surface of the first semiconductor layer; reshaping the spacer such that the a first sidewall of the reshaped spacer is slanted at a second angle relative to the top surface of the first semiconductor layer, in which the second angle is greater than the first angle; and performing a first epitaxy process to grow an epitaxy semiconductor layer in the recess after reshaping the spacer.Type: GrantFiled: November 13, 2020Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Wei Lee, Tsung-Yu Hung, Pang-Yen Tsai, Yasutoshi Okuno
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Patent number: 11715738Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a gate stack. The first semiconductor fin is over the substrate and includes a first germanium-containing layer and a second germanium-containing layer over the first germanium-containing layer. The first germanium-containing layer has a germanium atomic percentage higher than a germanium atomic percentage of the second germanium-containing layer. The gate stack is across the first semiconductor fin.Type: GrantFiled: July 27, 2022Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Yu Hung, Pei-Wei Lee, Pang-Yen Tsai
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Patent number: 11600577Abstract: A semiconductor device includes a substrate and a semiconductor layer. The substrate includes a planar portion and a plurality of pillars on a periphery of the planar portion. The pillars are shaped as rectangular columns, and corners of two of the pillars at the same side of the planar portion are aligned in a horizontal direction or a direction perpendicular to the horizontal direction. The semiconductor layer is disposed over the planar portion and between the pillars.Type: GrantFiled: October 13, 2020Date of Patent: March 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Wei Lee, Pang-Yen Tsai, Tsung-Yu Hung
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Publication number: 20220367525Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a gate stack. The first semiconductor fin is over the substrate and includes a first germanium-containing layer and a second germanium-containing layer over the first germanium-containing layer. The first germanium-containing layer has a germanium atomic percentage higher than a germanium atomic percentage of the second germanium-containing layer. The gate stack is across the first semiconductor fin.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Yu HUNG, Pei-Wei LEE, Pang-Yen TSAI
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Publication number: 20220359662Abstract: A semiconductor device according to the present disclosure includes a substrate including a plurality of atomic steps that propagate along a first direction, and a transistor disposed on the substrate. The transistor includes a channel member extending a second direction perpendicular to the first direction, and a gate structure wrapping around the channel member.Type: ApplicationFiled: July 22, 2022Publication date: November 10, 2022Inventors: Pei-Wei Lee, Yasutoshi Okuno, Pang-Yen Tsai
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Patent number: 11430867Abstract: A semiconductor device according to the present disclosure includes a substrate including a plurality of atomic steps that propagate along a first direction, and a transistor disposed on the substrate. The transistor includes a channel member extending a second direction perpendicular to the first direction, and a gate structure wrapping around the channel member.Type: GrantFiled: July 30, 2020Date of Patent: August 30, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Wei Lee, Yasutoshi Okuno, Pang-Yen Tsai
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Patent number: 11417684Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a gate stack. The first semiconductor fin is over the substrate and includes a first germanium-containing layer and a second germanium-containing layer over the first germanium-containing layer. The first germanium-containing layer has a germanium atomic percentage higher than a germanium atomic percentage of the second germanium-containing layer. The gate stack is across the first semiconductor fin.Type: GrantFiled: December 11, 2020Date of Patent: August 16, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Yu Hung, Pei-Wei Lee, Pang-Yen Tsai
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Publication number: 20220165847Abstract: The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.Type: ApplicationFiled: February 14, 2022Publication date: May 26, 2022Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.Inventors: Miao-Syuan FAN, Pei-Wei LEE, Ching-Hua LEE, Jung-Wei LEE