Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are presented. In embodiments the methods of manufacturing include depositing a first bonding layer on a first substrate, wherein the first substrate comprises a semiconductor substrate and a metallization layer. The first bonding layer and the semiconductor substrate are patterned to form first openings. A second substrate is bonded to the first substrate. After the bonding the second substrate, the second substrate is patterned to form second openings, at least one of the second openings exposing at least one of the first openings. After the patterning the second substrate, a third substrate is bonded to the second substrate, and after the bonding the third substrate, the third substrate is patterned to form third openings, at least one of the third openings exposing at least one of the second openings.

Abstract: Microelectromechanical devices and methods of manufacture are presented. Embodiments include bonding a mask substrate to a first microelectromechanical system (MEMS) device. After the bonding has been performed, the mask substrate is patterned. A first conductive pillar is formed within the mask substrate, and a second conductive pillar is formed within the mask substrate, the second conductive pillar having a different height from the first conductive pillar. The mask substrate is then removed.

Abstract: A semiconductor chip and a manufacturing method thereof are provided. The semiconductor chip includes: an array of pillar structures, disposed on a front surface of the semiconductor chip, and respectively including a ground pillar and multiple working pillars laterally spaced apart from and substantially parallel with a line portion of the ground pillar; and dummy pillar structures, disposed on the front surface of the semiconductor chip and laterally surrounding the pillar structures. Active devices formed inside the semiconductor chip are electrically connected to the working pillar. The ground pillars of the pillar structures and the dummy pillar structures are electrically connected to form a current pathway on the front surface of the semiconductor chip.

Abstract: A method of generating a first performance-data-library (for a standard-cell-library) includes: for each standard cell that includes multiple gates, sorting the gates into groups including searching for matched ones amongst the gates (matched gates), grouping corresponding matched gates into corresponding multiple member-gates, and (for unmatched ones of the gates having no other matched gate (unmatched gates)), grouping the unmatched gates into corresponding single-member groups; for each standard cell, generating a corresponding first volume of performance data including, for each group, discretely calculating the first volume of performance data, mapping the volume of performance data to the subject gate in the group, and, for each multimember group, mapping the volume of performance data to non-subject gates; and basing the first performance-data-library at least in part on the first volumes of performance data.

Abstract: Methods and apparatus for rating Uniform Resource Locators (URLs) are disclosed. The method includes determining a request size pertaining to a length of the URL to be rated and for generating a rating request message containing the URL. The rating request message is a DNS (domain name system) message if the request size is less than or equal to a predefined size limitation, and the rating request message is a HTTP (hypertext transfer protocol) message if the request size is greater than the predefined size limitation.