Patents by Inventor Pei-Wen Luo
Pei-Wen Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9905277Abstract: A memory system comprises a memory controller and a memory device having one or more memory ranks and multiple memory electrically connected to the one or more memory ranks. The memory controller includes at least one analysis module and at least one switching determination module. The analysis module analyzes states of multiple memory control commands corresponding to a particular memory rank to generate a control parameter. The switching determination module determines whether at least one switching command is sent according to the control parameter, a current operation mode of the particular memory rank, and an operation state of the particular memory rank. When the memory device receives a first switching command of the at least one command, the particular rank and at least one part of the memory internal circuits are switched from the normal voltage operation mode to the low voltage operation mode.Type: GrantFiled: October 21, 2015Date of Patent: February 27, 2018Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Pei-Wen Luo, Hsiu-Chuan Shih, Chi-Kang Chen, Ding-Ming Kwai, Cheng-Wen Wu
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Publication number: 20170003908Abstract: A memory system comprises a memory controller and a memory device having one or more memory ranks and multiple memory electrically connected to the one or more memory ranks. The memory controller includes at least one analysis module and at least one switching determination module. The analysis module analyzes states of multiple memory control commands corresponding to a particular memory rank to generate a control parameter. The switching determination module determines whether at least one switching command is sent according to the control parameter, a current operation mode of the particular memory rank, and an operation state of the particular memory rank. When the memory device receives a first switching command of the at least one command, the particular rank and at least one part of the memory internal circuits are switched from the normal voltage operation mode to the low voltage operation mode.Type: ApplicationFiled: October 21, 2015Publication date: January 5, 2017Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Pei-Wen LUO, Hsiu-Chuan SHIH, Chi-Kang CHEN, Ding-Ming KWAI, Cheng-Wen WU
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Patent number: 9472249Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.Type: GrantFiled: August 18, 2015Date of Patent: October 18, 2016Assignee: INTEL CORPORATIONInventors: Andre Schaefer, Jen-Chieh Yeh, Pei-Wen Luo
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Publication number: 20150357011Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.Type: ApplicationFiled: August 18, 2015Publication date: December 10, 2015Applicant: INTEL CORPORATIONInventors: ANDRE SCHAEFER, JEN-CHIEH YEH, PEI-WEN LUO
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Patent number: 9135982Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.Type: GrantFiled: December 18, 2013Date of Patent: September 15, 2015Assignee: INTEL CORPORATIONInventors: Andre Schaefer, Jen-Chieh Yeh, Pei-Wen Luo
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Publication number: 20150170729Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.Type: ApplicationFiled: December 18, 2013Publication date: June 18, 2015Inventors: ANDRE SCHAEFER, JEN-CHIEH YEH, PEI-WEN LUO
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Patent number: 8051394Abstract: A yield evaluating apparatus and a method thereof are provided. The yield evaluating apparatus includes a spatial correlation module. The spatial correlation module receives at least one process-related data and a plurality of circuit layouts and obtains a correlation coefficient between unit elements in the circuit layouts according to the process-related data. The spatial correlation module calculates a spatial correlation between elements in each of the circuit layouts according to the correlation coefficient and selects one of the circuit layouts according to the spatial correlations.Type: GrantFiled: November 3, 2008Date of Patent: November 1, 2011Assignees: Industrial Technology Research Institute, National Central UniversityInventors: Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen-Ching Wu
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Publication number: 20100088655Abstract: A yield evaluating apparatus and a method thereof are provided. The yield evaluating apparatus includes a spatial correlation module. The spatial correlation module receives at least one process-related data and a plurality of circuit layouts and obtains a correlation coefficient between unit elements in the circuit layouts according to the process-related data. The spatial correlation module calculates a spatial correlation between elements in each of the circuit layouts according to the correlation coefficient and selects one of the circuit layouts according to the spatial correlations.Type: ApplicationFiled: November 3, 2008Publication date: April 8, 2010Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, NATIONAL CENTRAL UNIVERSITYInventors: Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen-Ching Wu
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Publication number: 20070244686Abstract: A calibration method of a mixed mode simulation calibrates standard delay times in a standard delay format and includes obtaining a digital output circuit from a digital circuit, obtaining an analog output circuit from an analog circuit, performing a simulation on the digital output circuit connected to the analog output circuit to obtain an ideal output, obtaining a first delay time according to the standard delay times of the digital output circuit, performing a calibrative analog-to-digital mixed mode simulation using the first delay time to obtain an analog-to-digital mixed output, comparing the ideal output and the analog-to-digital mixed output to calibrate the first delay time, and calibrating the standard delay times of the digital output circuit according to the calibrated first delay time.Type: ApplicationFiled: July 7, 2006Publication date: October 18, 2007Inventors: Yaong-Jar Chang, Yung-Chieh Lin, Jung-Chi Ho, Pei-Wen Luo
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Patent number: 6950046Abstract: IC with built-in self-test and design method thereof. The IC comprises an SD-ADC and a Dft circuit. The Dft circuit uses a digital stimulus signal to solve the deadlock problem of the on-chip analog testing and avoid thermal noise. Moreover, according to the design method of the IC, circuits having different specification can use the Dft circuit without performance degradation for original SD-ADC.Type: GrantFiled: July 20, 2004Date of Patent: September 27, 2005Assignee: Industrial Technology Research InstituteInventors: Pei-Wen Luo, Yeong-Jar Chang, Jung-Chi Ho, Wen-Ching Wu
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Publication number: 20050174273Abstract: IC with built-in self-test and design method thereof. The IC comprises an SD-ADC and a Dft circuit. The Dft circuit uses a digital stimulus signal to solve the deadlock problem of the on-chip analog testing and avoid thermal noise. Moreover, according to the design method of the IC, circuits having different specification can use the Dft circuit without performance degradation for original SD-ADC.Type: ApplicationFiled: July 20, 2004Publication date: August 11, 2005Inventors: Pei-Wen Luo, Yeong-Jar Chang, Jung-Chi Ho, Wen-Ching Wu