Abstract: The invention provides a light spot scanning device, a scanning method thereof, and a medical cosmetology device, belonging to the technical field of medical cosmetology, comprising a laser and a collimating lens and a reflector arranged in sequence along the optical path transmission direction of the laser. The reflector is also connected with a driving member, the laser beam emitted by the laser forms a linear light spot through the collimating lens, and the reflector is driven to continuously rotate according to a preset path through the driving member. A plurality of linear light spots formed by the continuous rotation are sequentially overlapped on the light exiting side of the reflector to form a scanning linear light spot. Each time the reflector rotates, a group of linear light spots is formed. After continuous rotation, multiple groups of sequentially overlapping linear light spots are formed on the light exiting side of the reflector, called scanning linear light spots.

Abstract: A multi-write read-only memory array includes word common-source lines, bit lines, and sub-memory arrays. The word common-source lines include a first word common-source line and a second word common-source line. The bit lines include a first bit line and a second bit line. Each sub-memory array includes a first memory cell coupled to the first word common-source line and the first bit line, a second memory cell coupled to the first word common-source line and the second bit line, a third memory cell coupled to the second word common-source line and the second bit line, and a fourth memory cell coupled to the second word common-source line and the first bit line.

Abstract: A small-area high-efficiency read-only memory (ROM) array and a method for operating the same are provided. The small-area high-efficiency ROM array includes bit lines, word common-source lines, and sub-memory arrays. Each sub-memory array includes first, second, third, and fourth memory cells connected to a bit line and a word common-source line. All the memory cells are connected to the same word common-source line and respectively connected to different bit lines. Sharing the gate and the source can not only greatly reduce the overall layout area, but also effectively reduce the load of the memory array to achieve the high-efficiency reading and writing goal.

Abstract: A high-speed multi-write read only memory array includes word lines, select lines, bit lines, and sub-memory arrays. There are a first word line, a first select line, a second select line, a first bit line, a second bit line, a third bit line, and a fourth bit line. Each sub-memory array includes a first memory cell coupled to the first word line, the first select line, and the first bit line, a second memory cell coupled to the first word line, the first select line, and the second bit line, a third memory cell coupled to the first word line, the second select line, and the third bit line, and a fourth memory cell coupled to the first word line, the second select line, and the fourth bit line.

Abstract: An automatic processing device for liquid samples includes a sample region, a control module, an image identification device and a centrifuge. The sample region is configured to accommodate a plurality of centrifuge tubes. The control module includes a mechanical module. The mechanical module is configured to unscrew or tighten upper caps of the centrifuge tubes, and is configured to draw liquid from the centrifuge tubes or discharge liquid to the centrifuge tubes. The image identification device is coupled to the control module. The centrifuge is coupled to the control module. The centrifuge is configured to accommodate the centrifuge tubes and perform centrifugal treatment.

Abstract: A method includes: receiving a composite substrate including a first region and a second region, the composite substrate including a semiconductor substrate and an insulator layer over the semiconductor substrate; forming a trench through the insulator layer, the trench exposing a surface of the semiconductor substrate in the first region; growing an initial epitaxial layer in the trench and over an upper surface of the second region; thickening the initial epitaxial layer to form an epitaxial layer; forming a transistor layer over the epitaxial layer, the transistor layer including a first transistor and a second transistor in the first region and the second region, respectively; and forming an interconnect layer over the transistor layer and electrically coupling the first transistor to the second transistor.

Abstract: A backlight module and a display device are disclosed. The backlight module includes: a light guide plate that provides a surface light surface for the display panel and that has a first surface, a second surface, and a third surface, where the first surface is a light-emitting surface, and where the light incident surface connects the first and second surfaces together; a light source disposed on the light incident surface of the light guide plate and used to provide a linear light source for the light guide plate; a light absorbing and reflecting film layer disposed on the second surface of the light guide plate and used for absorbing light and reflecting blue light; and a first reflective sheet disposed on a side of the light absorbing and reflecting film layer facing away from the light guide plate.

Abstract: An infrared detector based on a CMOS process is provided.

Abstract: A small-area common-voltage multi-write non-volatile memory array includes word lines, select lines, common-voltage lines, and sub-memory arrays. The word lines include a first word line and a second word line. The select lines include a first select line. The common-voltage lines are directly coupled together. The common-voltage lines include a first common-voltage line and a second common-voltage line. Each sub-memory array includes a first non-volatile memory cell coupled to the first word line, the first select line, and the first common-voltage line and a second non-volatile memory cell coupled to the second word line, the first select line, and the second common-voltage line.

Abstract: A small-area common-voltage anti-fuse array includes word lines, select lines, common-voltage lines, and anti-fuse elements. The word lines include a first word line and a second word line. The select lines are perpendicular to the common-voltage lines and the word lines. The select lines include a first select line. The common-voltage lines are directly coupled together. The common-voltage lines include a first common-voltage line and a second common-voltage line. Each anti-fuse element includes a first anti-fuse memory cell coupled to the first word line, the first select line, and the first common-voltage line and a second anti-fuse memory cell coupled to the second word line, the first select line, and the second common-voltage line.

Abstract: The present application provides a treatment method and device for a waste plastic. A first aspect of the present application provides a treatment method for a waste plastic, including: firstly subjecting the waste plastic to a first pre-treatment to remove impurity and grease on a surface of the waste plastic, then subjecting the waste plastics to a second pre-treatment to convert a solid waste plastic into one in flow state; and finally, subjecting the waste plastic in flow state to a first cracking treatment and a second cracking treatment in sequence. Through the method provided in the present application, while cracking the waste plastic, chlorine element in the waste plastic may be removed by a multi-stage adsorption, which reduces chlorine content in the cracked oil, reduces pressure and burden in subsequent refining, and meets the limitation of the chlorine content in cracked products in downstream processes.

Abstract: A backlight module and a display device are disclosed. The backlight module includes: a light guide plate that provides a surface light surface for the display panel and that has a first surface, a second surface, and a third surface, where the first surface is a light-emitting surface, and where the light incident surface connects the first and second surfaces together; a light source disposed on the light incident surface of the light guide plate and used to provide a linear light source for the light guide plate; a light absorbing and reflecting film layer disposed on the second surface of the light guide plate and used for absorbing light and reflecting blue light; and a first reflective sheet disposed on a side of the light absorbing and reflecting film layer facing away from the light guide plate.

Abstract: A method includes: receiving a composite substrate including a first region and a second region, the composite substrate comprising a semiconductor substrate and an insulator layer over the semiconductor substrate; bonding a silicon layer to the composite substrate; depositing a capping layer over the silicon layer; forming a trench through the capping layer, the silicon layer and the insulator layer, the trench exposing a surface of the semiconductor substrate in the first region; growing an initial epitaxial layer in the trench; removing the capping layer to form an epitaxial layer from the silicon layer and the initial epitaxial layer; forming a transistor layer over the epitaxial layer, the transistor layer including a first transistor and a second transistor in the first region and the second region, respectively; and forming an interconnect layer over the transistor layer and electrically coupling the first transistor to the second transistor.

Abstract: An infrared detector with a multi-layer structure based on a CMOS process. A CMOS measuring circuit system and a CMOS infrared sensing structure in the infrared detector are both fabricated by using the CMOS process, and a CMOS manufacturing process comprises a metal interconnection process, a through hole process, an IMD process and an RDL process. In the infrared detector with the multi-layer structure, a first columnar structure comprises at least one layer of solid columnar structure and/or at least one layer of hollow columnar structure, a second columnar structure comprises at least one layer of solid columnar structure and/or at least one layer of hollow columnar structure, at least one hole-shaped structure is formed in an absorption plate, and the hole-shaped structure at least penetrates a dielectric layer in the absorption plate; and/or, at least one hole-shaped structure is formed in a beam structure.

Abstract: A fluid pressure proportional valve includes a valve body, a first core shaft, a second core shaft, and a driving motor. The valve body has a first orifice, a second orifice, a third orifice, and a receiving space having a valve port. The first and second core shafts are located in the receiving space. The first core shaft has a sealing portion, an abutting portion, and a flow channel. Under normal status, the sealing portion seals the valve port, and the second orifice communicates with the third orifice via the flow channel. When the driving motor drives the second core shaft to move along an axial direction, the second core shaft could seal the flow channel to block the communication between the second orifice and the third orifice and push the abutting portion of the first core shaft to depart from the valve port and the sealing portion, thereby communicating the first and the second orifices.

Abstract: An infrared detector with a multi-layer structure based on a CMOS process. A CMOS measuring circuit system and a CMOS infrared sensing structure in the infrared detector are both fabricated by using the CMOS process, and a CMOS manufacturing process comprises a metal interconnection process, a through hole process, an IMD process and an RDL process. In the infrared detector with the multi-layer structure, a first columnar structure comprises at least one layer of solid columnar structure and/or at least one layer of hollow columnar structure, a second columnar structure comprises at least one layer of solid columnar structure and/or at least one layer of hollow columnar structure, at least one hole-shaped structure is formed in an absorption plate, and the hole-shaped structure at least penetrates a dielectric layer in the absorption plate; and/or, at least one hole-shaped structure is formed in a beam structure.

Abstract: This application describes methods of inhibiting APOL1 and treating APOL1-mediated diseases comprising administering Compound I and/or a pharmaceutically acceptable salt thereof. The application also describes pharmaceutical compositions comprising Compound I and/or a pharmaceutically acceptable salt thereof.

Abstract: A remote direct memory access (RDMA) data transmission system includes a first network device in a first host and a second network device in a second host. The first network device may create a shared send queue (SSQ) used by a plurality of processes run by the first host, obtain an RDMA data transmission message of a first process from the SSQ, and encapsulate a first identifier corresponding to the first process into a first packet in which the RDMA data transmission message is encapsulated. The second network device is configured to encapsulate the first identifier into a second packet in which a feedback message is encapsulated.

Abstract: A small-area high-efficiency read-only memory (ROM) array and a method for operating the same are provided. The small-area high-efficiency ROM array includes bit lines, word common-source lines, and sub-memory arrays. Each sub-memory array includes first, second, third, and fourth memory cells connected to a bit line and a word common-source line. All the memory cells are connected to the same word common-source line and respectively connected to different bit lines. Sharing the gate and the source can not only greatly reduce the overall layout area, but also effectively reduce the load of the memory array to achieve the high-efficiency reading and writing goal.

Abstract: An infrared detector with a multi-layer structure based on a CMOS process. A CMOS measuring circuit system and a CMOS infrared sensing structure in the infrared detector are both fabricated by using the CMOS process, and a CMOS manufacturing process comprises a metal interconnection process, a through hole process, an IMD process and an RDL process. In the infrared detector with the multi-layer structure, a first columnar structure comprises at least one layer of solid columnar structure and/or at least one layer of hollow columnar structure, a second columnar structure comprises at least one layer of solid columnar structure and/or at least one layer of hollow columnar structure, at least one hole-shaped structure is formed in an absorption plate, and the hole-shaped structure at least penetrates a dielectric layer in the absorption plate; and/or, at least one hole-shaped structure is formed in a beam structure.