Patents by Inventor PEI-YI CHANG

PEI-YI CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnect Structure and Method of Forming Thereof
    Publication number: 20240413087
    Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.
    Type: Application
    Filed: July 31, 2024
    Publication date: December 12, 2024
    Inventors: Shu-Cheng Chin, Ming-Yuan Gao, Chen-Yi Niu, Yen-Chun Lin, Hsin-Ying Peng, Chih-Hsiang Chang, Pei-Hsuan Lee, Chi-Feng Lin, Chih-Chien Chi, Hung-Wen Su
  • Method of forming interconnect structure having a barrier layer
    Patent number: 12165975
    Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Cheng Chin, Ming-Yuan Gao, Chen-Yi Niu, Yen-Chun Lin, Hsin-Ying Peng, Chih-Hsiang Chang, Pei-Hsuan Lee, Chi-Feng Lin, Chih-Chien Chi, Hung-Wen Su
  • Barrier Free Tungsten Liner in Contact Plugs and The Method Forming the Same
    Publication number: 20240355740
    Abstract: A method includes forming a dielectric layer over a conductive feature, and etching the dielectric layer to form an opening. The conductive feature is exposed through the opening. The method further includes forming a tungsten liner in the opening, wherein the tungsten liner contacts sidewalls of the dielectric layer, depositing a tungsten layer to fill the opening, and planarizing the tungsten layer. Portions of the tungsten layer and the tungsten liner in the opening form a contact plug.
    Type: Application
    Filed: June 30, 2023
    Publication date: October 24, 2024
    Inventors: Feng-Yu Chang, Sheng-Hsuan Lin, Shu-Lan Chang, Kai-Yi Chu, Meng-Hsien Lin, Pei-Hsuan Lee, Pei Shan Chang, Chih-Chien Chi, Chun-I Tsai, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai, Syun-Ming Jang, Wei-Jen Lo
  • MOTHERBOARD WITH DUAL NETWORK CARD CONNECTORS AND LOW SIGNAL REFLECTIVITY
    Publication number: 20130049798
    Abstract: An exemplary motherboard includes a controller, and two different network card connectors. At least one of the two network card connectors is electronically connected to the controller via a resistor. A user of the motherboard may choose to use either the first network card connector, or the second network card connector, or the first network card connector and the second network card connector simultaneously.
    Type: Application
    Filed: November 20, 2011
    Publication date: February 28, 2013
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: PEI-YI CHANG, CHENG-CHUAH LIN
  • Electrical stimulator
    Patent number: D1052748
    Type: Grant
    Filed: February 5, 2023
    Date of Patent: November 26, 2024
    Assignee: GiMer Medical Company Limited
    Inventors: Cheng-Yung Tung, Ching-Tai Wang, Chi-Heng Chang, Pei-Yi Lin, Chia-Hsiung Peng