Patents by Inventor Pei-Ying Hsueh
Pei-Ying Hsueh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240133950Abstract: A test device is configured to test an on-chip clock controller having a debug function. The test device includes a scan chain and a test circuit. The scan chain includes N flip-flop circuit(s), each of which stores a first input signal as a storage signal, then stores a second input signal as the storage signal or keeps the current storage signal according to an input clock, and then output the storage signal. Since the first and second input signals are different, the outputted storage signal indicates whether the flip-flop circuit stores the second input signal or keeps the current storage signal according to the input clock under predetermined test setting, and indicates whether circuits under test (CUTs) for transmitting the input clock operate normally. The test circuit outputs an observation clock of the on-chip clock controller or an independent clock as the input clock according to the predetermined test setting.Type: ApplicationFiled: October 12, 2023Publication date: April 25, 2024Inventors: SHENG-PING YUNG, PEI-YING HSUEH
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Patent number: 11774497Abstract: The present invention discloses an isolation circuit having test mechanism. An isolation circuit component performs signal transmission when a signal that a control terminal receives has an enabling state and performs signal isolation when the signal has a disabling state. The test circuit includes a multiplexer and a control circuit. Under a shifting operation state in a test mode, the control circuit controls the multiplexer to select an operation input terminal to receive and output an isolation control signal having the enabling state to the control input terminal. Under a capturing operation state in the test mode, the control circuit controls the multiplexer to select a test input terminal to receive and output the test signal to the control input terminal. The control circuit further determines whether the isolation circuit performs signal transmission or signal isolation according to the signals at the data input terminal and the data output terminal.Type: GrantFiled: October 14, 2021Date of Patent: October 3, 2023Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Kuo-Kai Liu, Chih-Chieh Cheng, Pei-Ying Hsueh
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Publication number: 20220120812Abstract: The present invention discloses an isolation circuit having test mechanism. An isolation circuit component performs signal transmission when a signal that a control terminal receives has an enabling state and performs signal isolation when the signal has a disabling state. The test circuit includes a multiplexer and a control circuit. Under a shifting operation state in a test mode, the control circuit controls the multiplexer to select an operation input terminal to receive and output an isolation control signal having the enabling state to the control input terminal. Under a capturing operation state in the test mode, the control circuit controls the multiplexer to select a test input terminal to receive and output the test signal to the control input terminal. The control circuit further determines whether the isolation circuit performs signal transmission or signal isolation according to the signals at the data input terminal and the data output terminal.Type: ApplicationFiled: October 14, 2021Publication date: April 21, 2022Inventors: KUO-KAI LIU, CHIH-CHIEH CHENG, PEI-YING HSUEH
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Patent number: 11287472Abstract: A chip testing method including the following operations is disclosed: outputting a plurality of testing sequences to a plurality of scan chains by an encoding circuit; generating a plurality of scan output data according to the plurality of testing sequences by the plurality of scan chains; and determining whether an error exists in the plurality of scan chains or not according to the plurality of scan output data by a decoding circuit.Type: GrantFiled: September 22, 2020Date of Patent: March 29, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Sheng-Ping Yung, Pei-Ying Hsueh, Chun-Yi Kuo
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Publication number: 20210096180Abstract: A chip testing method including the following operations is disclosed: outputting a plurality of testing sequences to a plurality of scan chains by an encoding circuit; generating a plurality of scan output data according to the plurality of testing sequences by the plurality of scan chains; and determining whether the plurality of scan chains exist an error according to the plurality of scan output data by a decoding circuit.Type: ApplicationFiled: September 22, 2020Publication date: April 1, 2021Inventors: Sheng-Ping YUNG, Pei-Ying HSUEH, Chun-Yi KUO
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Patent number: 10698029Abstract: A chip includes one or more function input pads, a sequence generation circuit, one or more logic circuits, one or more scan chains, a selection circuit, and one or more sequence output pads. The function input pad is configured to receive a function sequence. The sequence generation circuit is configured to generate a diagnosis sequence. The logic circuit includes a plurality of logic gates, for responding to the function sequence and outputting one or more logic results. When enabled by the selection circuit, the scan chain outputs a response result in response to the logic result or a diagnosis result in response to the diagnosis sequence. The sequence output pad receives the diagnosis result when the scan chain responds to the diagnosis sequence.Type: GrantFiled: March 28, 2019Date of Patent: June 30, 2020Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Sheng-Ping Yung, Pei-Ying Hsueh, Chun-Yi Kuo
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Publication number: 20200124666Abstract: A chip includes one or more function input pads, a sequence generation circuit, one or more logic circuits, one or more scan chains, a selection circuit, and one or more sequence output pads. The function input pad is configured to receive a function sequence. The sequence generation circuit is configured to generate a diagnosis sequence. The logic circuit includes a plurality of logic gates, for responding to the function sequence and outputting one or more logic results. When enabled by the selection circuit, the scan chain outputs a response result in response to the logic result or a diagnosis result in response to the diagnosis sequence. The sequence output pad receives the diagnosis result when the scan chain responds to the diagnosis sequence.Type: ApplicationFiled: March 28, 2019Publication date: April 23, 2020Applicant: REALTEK SEMICONDUCTOR CORP.Inventors: Sheng-Ping Yung, Pei-Ying Hsueh, Chun-Yi Kuo
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Patent number: 9983264Abstract: A multiple defect diagnosis method includes: receiving a gate-level netlist of a chip, a plurality of test patterns and a plurality of test failure reports; deriving a plurality of seed nets from the gate-level netlist according to the plurality of test patterns and the plurality of test failure reports; utilizing a processor to compute similarity between the plurality of seed nets, and accordingly merging the plurality of seed nets to obtain a single seed net tree; and deriving at least one suspected seed net according to the single seed net tree.Type: GrantFiled: October 20, 2014Date of Patent: May 29, 2018Assignee: Realtek Semiconductor Corp.Inventors: Pei-Ying Hsueh, Chun-Yi Kuo, Chien-Mo Li, Chieh-Chih Che
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Patent number: 9213799Abstract: A systematic defect analyzing method, includes: partitioning physical sites into groups to obtain a plurality of groups of physical sites according to a plurality of physical features of a chip corresponding to different potential systematic defects; utilizing a processor to compute at least one defect probability of each group of physical sites; and deriving an analysis result according to the plurality of defect probabilities corresponding to the plurality of groups of physical sites.Type: GrantFiled: August 13, 2014Date of Patent: December 15, 2015Assignee: Realtek Semiconductor Corp.Inventors: Pei-Ying Hsueh, Chun-Yi Kuo, Chien-Mo Li, Po-Juei Chen
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Publication number: 20150204939Abstract: A multiple defect diagnosis method includes: receiving a gate-level netlist of a chip, a plurality of test patterns and a plurality of test failure reports; deriving a plurality of seed nets from the gate-level netlist according to the plurality of test patterns and the plurality of test failure reports; utilizing a processor to compute similarity between the plurality of seed nets, and accordingly merging the plurality of seed nets to obtain a single seed net tree; and deriving at least one suspected seed net according to the single seed net tree.Type: ApplicationFiled: October 20, 2014Publication date: July 23, 2015Inventors: Pei-Ying Hsueh, Chun-Yi Kuo, Chien-Mo Li, Chieh-Chih Che
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Publication number: 20150205907Abstract: A systematic defect analyzing method, includes: partitioning physical sites into groups to obtain a plurality of groups of physical sites according to a plurality of physical features of a chip corresponding to different potential systematic defects; utilizing a processor to compute at least one defect probability of each group of physical sites; and deriving an analysis result according to the plurality of defect probabilities corresponding to the plurality of groups of physical sites.Type: ApplicationFiled: August 13, 2014Publication date: July 23, 2015Inventors: Pei-Ying Hsueh, Chun-Yi Kuo, Chien-Mo Li, Po-Juei Chen