Patents by Inventor Pei-Yuan Chen

Pei-Yuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100277101
    Abstract: The present invention discloses an electronic ballast with dimming control from power line sensing for a fluorescent lamp, comprising: a line switching sensing circuit, used to generate a switching sensing signal by performing a voltage comparison operation on a DC voltage; an oscillating signal gating unit, used to gate an oscillating signal with a pulse signal to generate a gated oscillating signal, wherein the pulse width of the pulse signal is generated according to the switching sensing signal; and a non-overlapping driver, used to generate a high side driving signal and a low side driving signal according to the gated oscillating signal.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 4, 2010
    Inventors: Ko-Ming LIN, Yen-Ping WANG, Pei-Yuan CHEN, Wei-Chuan SU, Chia-Chieh HUNG, Jian-Shen LI
  • Publication number: 20100123501
    Abstract: “An active-load dominant circuit for common-mode glitch interference cancellation, biased between a first voltage potential and a second voltage potential with an accompanying common-mode glitch interferer. The active-load dominant circuit includes a pair of pull-up networks and a pair of active-load networks. The common-mode glitch interferer is cancelled out due to a symmetric structure of the pair of pull-up networks. At least one set signal and at least one reset signal are provided to a latch in response to a clock signal or a complemented clock signal. At least one of the set signal and the reset signal can be pulled up to the first voltage potential or pulled down to the second voltage potential. The voltage difference of the set signal and the reset signal is large enough for a latch.
    Type: Application
    Filed: November 18, 2008
    Publication date: May 20, 2010
    Inventors: Yen-Ping Wang, Yen-Hui Wang, Pei-Yuan Chen
  • Patent number: 7719325
    Abstract: An active-load dominant circuit for common-mode glitch interference cancellation, biased between a first voltage potential and a second voltage potential with an accompanying common-mode glitch interferer. The active-load dominant circuit includes a pair of pull-up networks and a pair of active-load networks. The common-mode glitch interferer is cancelled out due to a symmetric structure of the pair of pull-up networks. At least one set signal and at least one reset signal are provided to a latch in response to a clock signal or a complemented clock signal. At least one of the set signal and the reset signal can be pulled up to the first voltage potential or pulled down to the second voltage potential. The voltage difference of the set signal and the reset signal is large enough for a latch.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: May 18, 2010
    Assignee: Grenergy Opto, Inc.
    Inventors: Yen-Ping Wang, Yen-Hui Wang, Pei-Yuan Chen