Abstract: Atomic layer deposited (ALD) oxide semiconductors for integrated circuits are disclosed. In one aspect, an ALD process is used to form an oxide semiconductor channel formed from Indium Oxide (In2O3) on a transistor formed in a back end of line (BEOL) process. In further aspects, the thickness of the In2O3 is controlled to a desired thickness and annealed to reduce defects. Still further aspects of the present disclosure may use this process on a fin-based field-effect transistor (FinFET).

Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device are disclosed. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

Abstract: A method of forming single and few layer graphene on a quartz substrate in one embodiment includes providing a quartz substrate, melting a portion of the quartz substrate, diffusing a form of carbon into the melted portion to form a carbon and quartz mixture, and precipitating at least one graphene layer out of the carbon and quartz mixture.

Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device are disclosed. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

Abstract: A method of forming single and few layer graphene on a quartz substrate in one embodiment includes providing a quartz substrate, melting a portion of the quartz substrate, diffusing a form of carbon into the melted portion to form a carbon and quartz mixture, and precipitating at least one graphene layer out of the carbon and quartz mixture.

Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

Abstract: Disclosed are fully transparent nanowire transistors having high field-effect mobilities. The fully transparent nanowire transistors disclosed herein include one or more nanowires, a gate dielectric prepared from a transparent inorganic or organic material, and transparent source, drain, and gate contacts fabricated on a transparent substrate. The fully transparent nanowire transistors disclosed herein also can be mechanically flexible.

Abstract: Disclosed are fully transparent nanowire transistors having high field-effect mobilities. The fully transparent nanowire transistors disclosed herein include one or more nanowires, a gate dielectric prepared from a transparent inorganic or organic material, and transparent source, drain, and gate contacts fabricated on a transparent substrate. The fully transparent nanowire transistors disclosed herein also can be mechanically flexible.

Abstract: Field effect transistor devices comprising III-V semiconductors and organic gate dielectric materials, such dielectric materials as can afford flexibility in device design and fabrication.

Abstract: A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel.

Abstract: Disclosed are fully transparent nanowire transistors having high field-effect mobilities. The fully transparent nanowire transistors disclosed herein include one or more nanowires, a gate dielectric prepared from a transparent inorganic or organic material, and transparent source, drain, and gate contacts fabricated on a transparent substrate. The fully transparent nanowire transistors disclosed herein also can be mechanically flexible.

Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

Abstract: A method for forming a metal oxide semiconductor field-effect transistor (MOSFET) includes forming a III-V compound semiconductor on a substrate with the III-V compound semiconductor being doped with a first dopant type. The method further includes doping a first and second region of the III-V compound semiconductor with a second dopant type to form a drain and a source of the MOSFET. The method further includes forming a gate dielectric on the III-V compound semiconductor through atomic layer deposition. The method further includes applying a metal onto the dielectric to form a gate of the MOSFET. A MOSFET is also disclosed herein.

Abstract: Field effect transistor devices comprising III-V semiconductors and organic gate dielectric materials, such dielectric materials as can afford flexibility in device design and fabrication.

Abstract: A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel.

Abstract: A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel.

Abstract: A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel.

Abstract: The present invention provides a method for manufacturing a semiconductor device comprising a III-V semiconductor substrate, and an insulating layer deposited on the substrate by Atomic Layer Deposition (ALD). The use of ALD to deposit the insulating layer was found to facilitate the creation of active devices that avoid Fermi layer pinning. In addition, such insulating layer may be advantageously used as a passivation layer in III-V substrate based active devices and transistors.

Abstract: The present invention provides a method for manufacturing a semiconductor device comprising a III-V semiconductor substrate, and an insulating layer deposited on the substrate by Atomic Layer Deposition (ALD). The use of ALD to deposit the insulating layer was found to facilitate the creation of active devices that avoid Fermi layer pinning. In addition, such insulating layer may be advantageously used as a passivation layer in III-V substrate based active devices and transistors.