Patents by Inventor Pei-Feng Sun
Pei-Feng Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7432204Abstract: A wafer and the manufacturing and reclaiming methods thereof are disclosed. The wafer includes a semiconductor substrate and a protective layer formed on the surface of the semiconductor substrate. The reclaiming method of the wafer includes providing a wafer having a semiconductor substrate, a protective layer formed on the semiconductor substrate, and a polysilicon layer formed on the protective layer; and removing the polysilicon layer. The wafer and the reclaiming method of the wafer can prevent the substrate of the wafer from being destroyed during the reclaiming process and increase the reclaiming rate of the wafer.Type: GrantFiled: August 13, 2004Date of Patent: October 7, 2008Assignee: Mosel Vitelic, Inc.Inventors: Jen Chieh Chang, Yi Fu Chung, Pei-Feng Sun
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Patent number: 7282429Abstract: Embodiments of the invention provide a method of manufacturing a Schottky diode device. In one embodiment, the method includes: (a) providing a substrate; (b) sequentially forming a gate oxide layer and a polysilicon layer on the substrate; (c) partially oxidizing the polysilicon layer to form a poly oxide layer on the polysilicon layer; (d) forming and defining a photoresist layer on the poly oxide layer for exposing parts of the poly oxide layer; (e) etching the poly oxide layer, the polysilicon layer and the gate oxide layer via the photoresist layer for forming a poly oxide structure, a polysilicon structure and a gate oxide structure; and (f) removing the photoresist layer. The present invention introduces a poly oxide layer instead of the CVD oxide for preventing the photoresist lifting issue.Type: GrantFiled: August 19, 2005Date of Patent: October 16, 2007Assignee: Mosel Vitelic, Inc.Inventors: Shih-Chi Lai, Pei-Feng Sun, Yi Fu Chung, Jen Chieh Chang
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Publication number: 20060091589Abstract: The present invention relates to a monitoring method for a furnace apparatus. The monitoring method includes powering on the furnace apparatus to a specific power value; recording the rate of increase of the temperature of the furnace apparatus; and comparing the rate of increase of the temperature with a predetermined threshold value, wherein the furnace apparatus is to be replaced when the rate of increase of the temperature of the furnace apparatus is less than the predetermined threshold value.Type: ApplicationFiled: August 12, 2005Publication date: May 4, 2006Applicant: MOSEL VITELIC, INC.Inventors: Ming-Hung Chiu, Pei-Feng Sun, Kuo-Pin Pan, Sheng-Lung Wu
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Publication number: 20060046368Abstract: Embodiments of the invention provide a method of manufacturing a Schottky diode device. In one embodiment, the method includes: (a) providing a substrate; (b) sequentially forming a gate oxide layer and a polysilicon layer on the substrate; (c) partially oxidizing the polysilicon layer to form a poly oxide layer on the polysilicon layer; (d) forming and defining a photoresist layer on the poly oxide layer for exposing parts of the poly oxide layer; (e) etching the poly oxide layer, the polysilicon layer and the gate oxide layer via the photoresist layer for forming a poly oxide structure, a polysilicon structure and a gate oxide structure; and (f) removing the photoresist layer. The present invention introduces a poly oxide layer instead of the CVD oxide for preventing the photoresist lifting issue.Type: ApplicationFiled: August 19, 2005Publication date: March 2, 2006Applicant: Mosel Vitelic. Inc.Inventors: Shih-Chi Lai, Pei-Feng Sun, Yi Chung, Jen Chang
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Patent number: 6991994Abstract: A method for forming a trench having rounded corners in a semiconductor device comprises providing a substrate; forming a first pad oxide layer, a first silicon nitride layer, and a first oxide layer on the substrate sequentially; removing portions of the first oxide layer, the first silicon nitride layer, the first pad oxide layer, and the substrate to form at least one trench; and removing portions of the first oxide layer, the first silicon nitride layer, and the first pad oxide layer in the trench above an upper corner of the substrate in the trench. The substrate includes a lower corner at a bottom of the trench.Type: GrantFiled: February 3, 2004Date of Patent: January 31, 2006Assignee: Mosel Vitelic, Inc.Inventors: Pei-Feng Sun, Yi Fu Chung, Jen Chieh Chang
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Publication number: 20050248004Abstract: A wafer and the manufacturing and reclaiming methods thereof are disclosed. The wafer includes a semiconductor substrate and a protective layer formed on the surface of the semiconductor substrate. The reclaiming method of the wafer includes providing a wafer having a semiconductor substrate, a protective layer formed on the semiconductor substrate, and a polysilicon layer formed on the protective layer; and removing the polysilicon layer. The wafer and the reclaiming method of the wafer can prevent the substrate of the wafer from being destroyed during the reclaiming process and increase the reclaiming rate of the wafer.Type: ApplicationFiled: August 13, 2004Publication date: November 10, 2005Applicant: Mosel Vitelic, Inc.Inventors: Jen Chang, Yi Chung, Pei-Feng Sun
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Publication number: 20040253831Abstract: A method for forming a trench having rounded corners in a semiconductor device comprises providing a substrate; forming a first pad oxide layer, a first silicon nitride layer, and a first oxide layer on the substrate sequentially; removing portions of the first oxide layer, the first silicon nitride layer, the first pad oxide layer, and the substrate to form at least one trench; and removing portions of the first oxide layer, the first silicon nitride layer, and the first pad oxide layer in the trench above an upper corner of the substrate in the trench. The substrate includes a lower corner at a bottom of the trench.Type: ApplicationFiled: February 3, 2004Publication date: December 16, 2004Applicant: MOSEL VITELIC, INC.Inventors: Pei-Feng Sun, Yi Fu Chung, Jen Chieh Chang
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Patent number: 6828196Abstract: Embodiments of the present invention relate to a process for filling a trench structure of a semiconductor device to prevent formation of voids in the trench structure so as to minimize current leakage and provide excellent electrical properties. In one embodiment, a process for filling a trench of a semiconductor device comprises providing a semiconductor substrate; forming a silicon nitride layer on the semiconductor substrate; forming an oxide layer on the silicon nitride layer; partially removing the oxide layer, the silicon nitride layer and the semiconductor substrate to form at least one trench; forming a sacrificial oxide layer on sidewalls of the trench; removing the sacrificial oxide layer; performing an etching procedure to remove portions of the silicon nitride layer protruding from the sidewalls of the trench so as to form substantially even sidewalls of the trench; and forming a trench-fill layer to fill the trench and deposit on the oxide layer.Type: GrantFiled: August 28, 2003Date of Patent: December 7, 2004Assignee: Mosel Vitelec, Inc.Inventors: Pei-Feng Sun, Shih-Chi Lai, Mao-Song Tseng, Yi-Fu Chung
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Publication number: 20040166635Abstract: Embodiments of the present invention relate to a process for filling a trench structure of a semiconductor device to prevent formation of voids in the trench structure so as to minimize current leakage and provide excellent electrical properties. In one embodiment, a process for filling a trench of a semiconductor device comprises providing a semiconductor substrate; forming a silicon nitride layer on the semiconductor substrate; forming an oxide layer on the silicon nitride layer; partially removing the oxide layer, the silicon nitride layer and the semiconductor substrate to form at least one trench; forming a sacrificial oxide layer on sidewalls of the trench; removing the sacrificial oxide layer; performing an etching procedure to remove portions of the silicon nitride layer protruding from the sidewalls of the trench so as to form substantially even sidewalls of the trench; and forming a trench-fill layer to fill the trench and deposit on the oxide layer.Type: ApplicationFiled: August 28, 2003Publication date: August 26, 2004Applicant: MOSEL VITELIC, INC.Inventors: Pei-Feng Sun, Shih-Chi Lai, Mao-Song Tseng, Yi-Fu Chung
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Publication number: 20040112290Abstract: An apparatus for forming a film on a wafer in the semiconductor process is provided. The apparatus includes an inner part containing a susceptor for mounting thereon the wafer, and an outer part covering the inner part. There are an inlet and an outlet between the inner part and the outer part and gases can flow in and out through them. A special gas-feeding pipe is partially mounted inside the inlet. The gases are ejected from the gas-feeding pipe and toward the outer part instead of the inner part. Hence, the temperature difference between the gases and the inner part is diminished and the film adhered to the inner part will not peel to form particles. It reduces the contamination problem. A gas-feeding method is also provided according to the present apparatus.Type: ApplicationFiled: November 24, 2003Publication date: June 17, 2004Applicant: Mosel Vitelic, Inc.Inventors: Jui-Ping Li, Pei-Feng Sun, Ching-Cheng Hsieh, Yang-Nan Liu
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Patent number: 6492248Abstract: A few-particle-induced low-pressure TEOS process is disclosed. First, a lot of semiconductor substrates are arranged on a boat and transferred into a TEOS reactor. Silicon oxide films are then deposited on the semiconductor substrates by performing a low-pressure TEOS process. Before the substrates are sent out of the reactor, an annealing process is performed by injecting oxygen gas into the reactor to solidify the oxide films on the corners of the boat's flanges.Type: GrantFiled: June 26, 2001Date of Patent: December 10, 2002Assignee: Mosel Vitelic Inc.Inventors: Jen Chieh Chang, Yi Fu Chung, Ching-Cheng Hsieh, Pei-Feng Sun
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Publication number: 20020058398Abstract: A few-particle-induced low-pressure TEOS process is disclosed. First, a lot of semiconductor substrates are arranged on a boat and transferred into a TEOS reactor. Silicon oxide films are then deposited on the semiconductor substrates by performing a low-pressure TEOS process. Before the substrates are sent out of the reactor, an annealing process is performed by injecting oxygen gas into the reactor to solidify the oxide films on the corners of the boat's flanges.Type: ApplicationFiled: June 26, 2001Publication date: May 16, 2002Inventors: Jen Chieh Chang, Yi Fu Chung, Ching-Cheng Hsieh, Pei-Feng Sun
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Publication number: 20020001850Abstract: A method for automatically adjusting a concentration of a solution having a first component and a second component, used in a semiconductor manufacturing process, includes the steps of (a) providing target concentrations of the first component and the second component, (b) adjusting the concentration of the solution based on the first component by adding a first spiking amount of the first component during a first spiking time interval, and (c) adjusting the first spiking amount of the first component until a first deviation between an actual concentration of the first component and the target concentration of the first component is smaller than a first specific percentage.Type: ApplicationFiled: May 5, 1999Publication date: January 3, 2002Inventors: JUI-PING LI, CHIEN-HUNG CHEN, PEI-FENG SUN, MAY-JANE CHEN
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Patent number: 6147013Abstract: A method of LPCVD silicon nitride deposition for decreasing particles is disclosed. First, a silicon nitride layer is formed on a semiconductor substrate by LPCVD. Next, low gas flow rate purging step and cycle purging step are executed sequentially. Finally, the semiconductor substrate is taken out from the LPCVD tube. The key point of this invention is decreasing the gas flow rate of purging and cycle purging by inputting nitrogen gas slowly. Thereby the substrate surface contamination problem induced by conventional method can be avoided.Type: GrantFiled: January 26, 1999Date of Patent: November 14, 2000Assignee: Mosel Vitelic Inc.Inventors: Pei-Feng Sun, Ching-Cheng Hsieh, Chien-Hung Chen, May-Jane Chen