Patents by Inventor Peiheng ZHANG

Peiheng ZHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11971486
    Abstract: A superconducting nanowire photon detection array adjusts a number of the array elements, a lens array that 1) splits transmitted lights into multiple beams that equals the number of the array elements, and are converged in to a superconducting nanowire detection area; 2) a pulsed laser detects a surface of an object, transmits reflected different light pulses by the surface of the object through the lens array, and records a round-trip time of each photon; 3) collects the photons detected by each array element, takes the array elements as pixels and calculates a gray value of the pixels; and 4) plots a gray-scale image by taking the pixels as pixel points, calculates a distance between the object and the pixel points, and reconstructs a three-dimensional image of the object.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: April 30, 2024
    Assignee: NANJING UNIVERSITY
    Inventors: Labao Zhang, Rui Yin, Biao Zhang, Shuya Guo, Jingrou Tan, Rui Ge, Lin Kang, Peiheng Wu
  • Patent number: 10229087
    Abstract: A method for integrating a many-core processor system with a network router comprises a subnet division step used for dividing an on-chip network into network requests in multiple subnet balance chips, and a network interface device deployment step used for deploying at least one network interface device in a subnet in a distributed mode in order to guarantee optimization of the connectivity between the deployed network interface device and the processor cores in the subnets and to implement rapid data exchange of the on-chip network or the inter-chip network. A many-core processor system integrated with a network router comprises a network router used for network interfacing and data exchange, and comprising multiple network interface devices embedded into the on-chip network in a distributed mode.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: March 12, 2019
    Assignee: INSTITUTE OF COMPUTING TECHNOLOGY OF THE CHINESE ACADEMY OF SCIENCES
    Inventors: Ninghui Sun, Zheng Cao, Qiang Li, Xiaoli Liu, Xiaobing Liu, Xuejun An, Peiheng Zhang, En Shao
  • Publication number: 20170147528
    Abstract: The present invention discloses a method for integrating a many-core processor system with a network router. The method comprises a subnet division step used for dividing an on-chip network into network requests in multiple subnet balance chips, and a network interface device deployment step used for deploying at least one network interface device in a subnet in a distributed mode in order to guarantee optimization of the connectivity between the deployed network interface device and the processor cores in the subnets and to implement rapid data exchange of the on-chip network or the inter-chip network. The present invention also discloses a many-core processor system integrated with a network router. The system comprises a network router used for network interfacing and data exchange, and comprising multiple network interface devices embedded into the on-chip network in a distributed mode.
    Type: Application
    Filed: March 12, 2015
    Publication date: May 25, 2017
    Inventors: Ninghui SUN, Zheng CAO, Qiang LI, Xiaoli LIU, Xiaobing LIU, Xuejun AN, Peiheng ZHANG, En SHAO