Abstract: Embodiments of the present application provide a memory array circuit, a memory array layout and a verification method. The memory array circuit includes: M word lines (WLs); M WL break nodes, each being configured to separate a corresponding one of the WLs into a first WL pin and a second WL pin; N bit lines (BLs); and N BL break nodes, each being configured to separate a corresponding one of the BLs into a first BL pin and a second BL pin, wherein the M and the N each are a positive even number.

Abstract: The present disclosure provides a standard cell template and a semiconductor structure. The standard cell template includes a first well region and a second well region, arranged along a first direction; a first gate pattern, located in the first well region and extending along the first direction, for defining a first gate; a second gate pattern, located in the second well region and extending along the first direction, for defining a second gate; and a gate electrical connection pattern, located between the first gate pattern and the second gate pattern, for defining a gate electrical connection structure; where the gate electrical connection structure is arranged on the same layer as the first gate and the second gate to electrically connect the first gate and/or the second gate.

Abstract: Embodiments of the present application provide a memory array circuit, a memory array layout and a verification method. The memory array circuit includes: M word lines (WLs); M WL break nodes, each being configured to separate a corresponding one of the WLs into a first WL pin and a second WL pin; N bit lines (BLs); and N BL break nodes, each being configured to separate a corresponding one of the BLs into a first BL pin and a second BL pin, wherein the M and the N each are a positive even number.

Abstract: The disclosure provides a semiconductor structure, a layout of the semiconductor structure and a semiconductor device. The semiconductor structure includes: a plurality of first conductive layers which are spaced; a plurality of capacitor banks, and the capacitor bank being on the first conductive layer in one-to-one correspondence and the capacitor bank including at least a capacitor, each of the capacitor including a lower electrode layer, a capacitance dielectric layer and an upper electrode layer stacked from bottom to top; a capacitor plate, which is on each of the upper electrode layer; and a second conductive layer, which is above the capacitor plate and connected with the capacitor plate.

Abstract: The present disclosure provides a standard cell template and a semiconductor structure. The standard cell template includes a first well region and a second well region, arranged along a first direction; a first gate pattern, located in the first well region and extending along the first direction, for defining a first gate; a second gate pattern, located in the second well region and extending along the first direction, for defining a second gate; and a gate electrical connection pattern, located between the first gate pattern and the second gate pattern, for defining a gate electrical connection structure; where the gate electrical connection structure is arranged on the same layer as the first gate and the second gate to electrically connect the first gate and/or the second gate.