Patents by Inventor Pei-Liang Wang

Pei-Liang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978641
    Abstract: A method for manufacturing a semiconductor structure includes: forming a semiconductor device on a main region of the device substrate, the device substrate having a peripheral region surrounding the main region; forming a first filling layer on the peripheral region of the device substrate; forming a second filling layer over the first filling layer and the semiconductor device after forming the first filling layer, the second filling layer having a polishing rate different from that of the first filling layer; performing a planarization process over the second filling layer to remove a portion of the second filling layer so that a remaining portion of the second filling layer has a planarized surface opposite to the device substrate; and bonding the device substrate to a carrier substrate through the first filling layer and the remaining portion of the second filling layer.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Yu Chou, Yen-Yu Chen, Meng-Ku Chen, Shiang-Bau Wang, Tze-Liang Lee
  • Publication number: 20240074041
    Abstract: A circuit board includes a substrate and a metallic layer. A first area and at least one second area are defined on a portion of the substrate, the second area is located outside the first area. The metallic layer includes first test lines disposed on the first area and second test lines disposed on the second area. A first test pad of each of the first test lines has a first width, and a second test pad of each of the second test lines has a second width. The second width is greater than the first width such that probes of an electrical testing tool can contact the first and second test pads on the circuit board correctly during electrical testing.
    Type: Application
    Filed: August 16, 2023
    Publication date: February 29, 2024
    Inventors: Gwo-Shyan Sheu, Kuo-Liang Huang, Hsin-Hao Huang, Pei-Wen Wang, Yu-Chen Ma
  • Patent number: 8319110
    Abstract: A dual-layer flexible printed circuit is disclosed. The dual-layer flexible printed circuit includes an inner flexible printed circuit and an outer flexible printed circuit which overlaps the inner flexible printed circuit. The inner flexible printed circuit can be bent and forms a protrusion offset from the outer flexible printed circuit. The dual-layer flexible printed circuit further includes a fixing element to secure the protrusion to prevent the protrusion from extruding along a longitudinal direction of the dual-layer flexible printed circuit.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: November 27, 2012
    Assignee: Chi Mei Communication Systems, Inc.
    Inventor: Pei-Liang Wang
  • Publication number: 20110114370
    Abstract: A dual-layer flexible printed circuit is disclosed. The dual-layer flexible printed circuit includes an inner flexible printed circuit and an outer flexible printed circuit which overlaps the inner flexible printed circuit. The inner flexible printed circuit can be bent and forms a protrusion offset from the outer flexible printed circuit. The dual-layer flexible printed circuit further includes a fixing element to secure the protrusion to prevent the protrusion from extruding along a longitudinal direction of the dual-layer flexible printed circuit.
    Type: Application
    Filed: June 11, 2010
    Publication date: May 19, 2011
    Applicant: CHI MEI COMMUNICATION SYSTEMS, INC.
    Inventor: PEI-LIANG WANG