Abstract: The present invention discloses compounds of Formula (I), or pharmaceutically acceptable salts, which inhibit the cellular entry of hepatitis B virus (HBV) and/or hepatitis D virus (HDV) or interfere with the function of the life cycle of HBV and/or HDV and are also useful as antiviral agents. The present invention further relates to pharmaceutical compositions comprising the aforementioned compounds for administration to a subject suffering from HBV and/or HDV infection. The invention also relates to methods of treating an HBV and/or HDV infection in a subject by administering a pharmaceutical composition comprising the compounds of the present invention.

Abstract: Applications of CX-5461 in preparing a medicine for treating renal transplant immune rejection and a medicine for treating immune rejection after renal transplantation are provided in the present disclosure. CX-5461 significantly reduces immune rejection in renal transplantation, and is used as a new immunosuppressant to treat renal allograft rejection, especially the acute rejection after renal transplantation.

Abstract: Embodiments of the disclosure provide a recognition method, apparatus, device, and storage medium and relates to the field of artificial intelligence technology. The method includes obtaining a second decision-making threshold of a feature-matching model in a target scenario by joint testing of the feature-matching model and auxiliary detection model. The method takes into full consideration the mutual influence between different algorithm models in a scenario when multiple algorithm models are used for facial recognition. Compared to manually setting a decision-making threshold for each algorithm model independently, the methods in the disclosure are more adaptable to changing scenarios and scenarios with multiple models used in facial recognition. This improves the accuracy and efficiency of the obtained decision-making thresholds, thereby enhancing the accuracy of multi-model facial recognition.

Abstract: In certain embodiments, the present invention provides amplification methods in which nucleotide tag(s) and, optionally, a barcode nucleotide sequence are added to target nucleotide sequences. In other embodiments, the present invention provides a microfluidic device that includes a plurality of first input lines and a plurality of second input lines. The microfluidic device also includes a plurality of sets of first chambers and a plurality of sets of second chambers. Each set of first chambers is in fluid communication with one of the plurality of first input lines. Each set of second chambers is in fluid communication with one of the plurality of second input lines. The microfluidic device further includes a plurality of first pump elements in fluid communication with a first portion of the plurality of second input lines and a plurality of second pump elements in fluid communication with a second portion of the plurality of second input lines.

Abstract: A trusted anonymous voting method includes: performing a hash operation on original voting content to obtain a hash output including a commitment value cvi; blinding the commitment value cvi based on information of other voters to obtain commitment value tuples {tilde over (c)} and {tilde over (x)}; signing the commitment value tuple {tilde over (c)} by using an ESDSA to obtain a signature tuple {tilde over (s)}; and establishing a vote tuple ({tilde over (c)}, {tilde over (s)}, {tilde over (d)}) based on the commitment value tuple {tilde over (c)}, the signature tuple {tilde over (s)} and a signature tuple {acute over (d)} of other voters, and uploading the vote tuple (?, ?, {acute over (d)}) and the commitment value tuple {tilde over (x)} to the blockchain, where signature tuple {tilde over (d)} is generated in a case that other voters verify the signature tuple {tilde over (s)} and the signature tuple {tilde over (s)} passes the verification, and the commitment value tuple {tilde over (x)} is used to decry

Abstract: Provided are a device and method for detecting a fitting degree of a connecting rod bushing by an ultrasonic wave. A big head hole fixture comprises multiple positioning blocks, and the positioning blocks in a transverse section have a common point; an ultrasonic probe is capable of moving up-down and left-right and rotating; a center of the ultrasonic probe, a center of the big hole fixture and a center of a connecting rod body fixture are located on a straight line; when the device works, a connecting rod is positioned and then the fitting degree of the connecting rod bushing is detected; the multiple positioning blocks are capable of moving and contacting with an inner wall of a big head hole, the connecting rod body fixture is capable of moving and clamping the connecting rod and the ultrasonic probe is capable of moving to contact with the connecting rod bushing.

Abstract: Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.

Abstract: Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.

Abstract: Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.

Abstract: A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET (304) to n gates of the SFET. The IGRs have zigzagged central portions where each SFET gate runner is coupled via the IGRs to two MFET gate runners. The zigzagged central portions provide barriers that block parasitic leakage paths, between sources of the SFET and sources of the MFET, for all IGRs except the outboard sides of the first and last IGRs. These may be blocked by increasing the body doping in regions surrounding the remaining leakage paths. The IGRs have substantially no source regions.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure (100) includes a trench gate structure (114), a lateral gate structure (118), a body region (124) having a first conductivity type, a drain region (125) and first and second source regions (128, 130) having a second conductivity type. The first and second source regions (128, 130) are formed within the body region (124). The drain region (125) is adjacent to the body region (124) and the first source region (128) is adjacent to the trench gate structure (114), wherein a first portion of the body region (124) disposed between the first source region (128) and the drain region (125) is adjacent to the trench gate structure (114). A second portion of the body region (124) is disposed between the second source region (130) and the drain region (125), and the lateral gate structure (118) is disposed overlying the second portion of the body region (124).

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure (100) includes a trench gate structure (114), a lateral gate structure (118), a body region (124) having a first conductivity type, a drain region (125) and first and second source regions (128, 130) having a second conductivity type. The first and second source regions (128, 130) are formed within the body region (124). The drain region (125) is adjacent to the body region (124) and the first source region (128) is adjacent to the trench gate structure (114), wherein a first portion of the body region (124) disposed between the first source region (128) and the drain region (125) is adjacent to the trench gate structure (114). A second portion of the body region (124) is disposed between the second source region (130) and the drain region (125), and the lateral gate structure (118) is disposed overlying the second portion of the body region (124).

Abstract: A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

Abstract: A high voltage vertical field effect transistor device (101) is fabricated in a substrate (102, 104) using angled implantations (116, 120) into trench sidewalls formed above recessed gate poly layers (114) to form self-aligned N+ regions (123) adjacent to the trenches and along an upper region of an elevated substrate. With a trench fill insulator layer (124) formed over the recessed gate poly layers (114), self-aligned P+ body contact regions (128) are implanted into the elevated substrate without counter-doping the self-aligned N+ regions (123), and a subsequent recess etch removes the elevated substrate, leaving self-aligned N+ source regions (135-142) and P+ body contact regions (130-134).

Abstract: A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

Abstract: A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

Abstract: A trench gate transistor is formed from a semiconductor substrate with its upper surface covered in an oxide dielectric layer. The trench gate transistor has a drain region, a body region, source region and a trench lined with a gate insulator that electrically insulates a conductive gate electrode formed in the trench from the body region. The body region has a sloping upper surface that extends away from the trench towards the drain region. The sloping upper surface is formed by exposing the oxide dielectric layer to an oxidized atmosphere, through an opening in a mask, so as to form a dielectric region. The dielectric region includes the oxide dielectric layer and a sacrificial area of the semiconductor substrate.

Abstract: A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET (304) to n gates of the SFET. The IGRs have zigzagged central portions where each SFET gate runner is coupled via the IGRs to two MFET gate runners. The zigzagged central portions provide barriers that block parasitic leakage paths, between sources of the SFET and sources of the MFET, for all IGRs except the outboard sides of the first and last IGRs. These may be blocked by increasing the body doping in regions surrounding the remaining leakage paths. The IGRs have substantially no source regions.

Abstract: A high voltage vertical field effect transistor device (101) is fabricated in a substrate (102, 104) using angled implantations (116, 120) into trench sidewalls formed above recessed gate poly layers (114) to form self-aligned N+ regions (123) adjacent to the trenches and along an upper region of an elevated substrate. With a trench fill insulator layer (124) formed over the recessed gate poly layers (114), self-aligned P+ body contact regions (128) are implanted into the elevated substrate without counter-doping the self-aligned N+ regions (123), and a subsequent recess etch removes the elevated substrate, leaving self-aligned N+ source regions (135-142) and P+ body contact regions (130-134).

Abstract: Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.